Verilog code for Implementation of 5 stage pipelined processor that can perform Shift Right Arithmatic and Move Instructions Project was implemented in a modular manner, verilog description of data path and control path are realised separately, since we are dealing with 2 instructions, In this case Control path would be trivial so it was implemented in main processor block it self. Every main components required for implementation of processor's Datapath were made seperately and they were instantiated in the main processor module. This processor was tested through a test bench which was also included in the repository.

Purpose of each file in the repository

• execute.v- ALU of the processor which performs only shifting(since thats the only requirement in this scenario)
• idex.v- Pipeline register between Instruction Decode(ID) & Execute(EX) stages
• ifid.v- Pipeline register between Instruction Fetch(IF) & Instruction Decode(ID) stages
• instr_fetch.v- Instruction Fetcher for process from Instruction Memory
• instr_mem.v- Instruction memory for the processor
• main_proc.v- Main processor implementation where all the other modules are instantiated and connections are made
• main_proc_tb- Test bench for Main processor
• my_mux.v- Mulitplexer implementation for making decisions
• reg_file.v- Register bank for the processor
• regsel.v- Multiplexer that selects a bus of width 2, It's used for Write Backs