Very basic starter assignment to test proficiency in C/C++ abilities. A simple program to analyze given benchmark instruction traces

Implement dependency tracking and forwarding for a 5-stage superscalar pipeline, with branch prediction. This was a simulator to test performance (CPI) on an in-order pipelined processor.

Implement an Out of Order processor simulation. Evaluate performance using a ROB and RAT for register renaming (Tomasulo’s Algorithm). Also implement a small fully-associative data cache with LRU replacement policy.

Implement a multilevel cache and DRAM system to model timing and performance. Also simulate multi-core shared cache access with writeback. Cache model includes multiple replacement policy options.

Details of each assignment are in the respective pdf handouts.