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verilator's Issues

TinyLibrary/RapidJSON Not Distributed

The tiny library and rapidjson folders are empty which causes the build to fail.

I simply downloaded the repositories and placed the files in the respective folders but it would be nice if the documentation instructed this.

Tiny Process Library is empty

Hi, I failed to build this and in the make part gives me this error :

In file included from ../Verilator.cpp:96:
../V4VhdlFrontend.h:6:10: fatal error: tiny-process-library/process.hpp: No such file or directory
 #include "tiny-process-library/process.hpp"
          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[2]: *** [../Makefile_obj:293: Verilator.o] Error 1
make[2]: Leaving directory '/home/mani/svancau_verilator/svancau/verilator/verilator/src/obj_dbg'
make[1]: *** [Makefile:70: ../bin/verilator_bin_dbg] Error 2
make[1]: Leaving directory '/home/mani/svancau_verilator/svancau/verilator/verilator/src'
make: *** [Makefile:229: verilator_exe] Error 2

And I did the thing you said in another comment ( git submodule update --init --recursive --remote) but still there's nothing in the tiny process library. What should i do? Is it because it's still not workable? Thanks in advance for any help.

Mixed Language Failing

I have successfully ran the VHDL and verilog examples but I am now looking at mixing languages.

I modified the pwm.vhd file to instantiate a simple inverter written in verilog. I can Verilate the inverter.v and pwm.vhd files fine but when I include the pwm_top.vhd file the process fails with the following message:

** Fatal: tree kind T_COMPONENT does not have item I_DECLS
[0x55b5f9d61021] ../src/object.c:58 object_lookup_failed
[0x55b5f9d2da17] ../src/tree.c:636 tree_decls
[0x55b5f9d5b83c] ../src/json.c:988 dump_decls
[0x55b5f9d5acd7] ../src/json.c:574 dump_decl
[0x55b5f9d5b864] ../src/json.c:990 dump_decls
[0x55b5f9d5ca34] ../src/json.c:1003 trees_to_json
[0x55b5f9d5cca4] ../src/json.c:1106 dump_json
[0x55b5f9d115d0] ../src/nvc.c:181 process_command
[0x55b5f9d0fd16] ../src/nvc.c:1061 main
%Error: nvc failed to parse one of your input files

Do you have any pointers on where I might be going wrong?

It would be super useful to be able to do mixed VHDL and verilog simulation so I am excited to see this project.

Thanks in advance for any help you could provide.

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