This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.

The project is split into Five separate modules that make up the AES. Each module has been written in a Verilog file (.v) and has been instantiated in the 'main' module. The input data and key (each 128-bit long) need to be given through a test bench. This project was made with the Xilinx Spartan 3E FPGA in mind.