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When I try to synthesize the Neo430 on Quartus, I can't get it to compile. I'm following the tutorial in the pdf and I'm on step 8. I get a few errors at this step as shown below:

Is there any way you can help me fix these?
Thanks

On page 39 of the NEO430.pdf, I think you meant to say "stack" where you have heap:

3.1.2. Dynamic Memory
The remaining memory – so the memory after the .data section until the end of the RAM – is used for the
dynamic data during run time. This data includes the stack and the heap. The stack grows from the end of the memory down to the end of the .data section. The heap grows from the end of the .data section up to the end of the memory. Make sure there is no collision between the heap and the stack when using dynmic
memory allocation!

Hi Stephan,

really great work with this MSP430 implementation!
On the repo I found only one simple testbench. Are there more advacned TBs also available?

Thanks in advance.

Best Regards,
Andreas

If you changed the file:
https://github.com/stnolting/neo430/blob/master/sw/common/Makefile#L32

to

BIN_PATH ?= /mnt/c/msp430-gcc-6.4.0.32_linux64/bin

It would make it easier for the user to override the directory where the msp430-elf-gcc executable is found. On linux they can just set the path using:

$ export BIN_PATH=/home/joe_user/ti_7/ccsv7/tools/compiler/msp430-gcc-6.2.1.16_linux64/bin
$ cd blink_led/
$ make clean all

Memory utilization:
   text	   data	    bss	    dec	    hex	filename
    590	      0	      0	    590	    24e	main.elf
Installing application image to rtl/core/neo430_application_image.vhd
Final executable size (bytes):
596
$ 

Building code that uses the unit64_u defined in neo430.h I get compiler warnings.

To me it looks like there is a typo in the definition of uint64_u

When I make the following change the compiler warning goes away....

diff --git a/sw/lib/neo430/include/neo430.h b/sw/lib/neo430/include/neo430.h
index 20b21bf..fe8dd49 100644
--- a/sw/lib/neo430/include/neo430.h
+++ b/sw/lib/neo430/include/neo430.h
@@ -44,11 +44,11 @@
 // ----------------------------------------------------------------------------
 union uint16_u { uint16_t uint16; uint8_t  uint8[ sizeof(uint16_t)/1]; };
 union uint32_u { uint32_t uint32; uint16_t uint16[sizeof(uint32_t)/2]; uint8_t  uint8[ sizeof(uint32_t)/1]; };
-union uint64_u { uint64_t uint64; uint32_t uint32[sizeof(uint64_t)/4];  uint16_t uint16[sizeof(uint64_t)/2]; uint8_t uint8[sizeof(uint32_t)/1]; };
+union uint64_u { uint64_t uint64; uint32_t uint32[sizeof(uint64_t)/4];  uint16_t uint16[sizeof(uint64_t)/2]; uint8_t uint8[sizeof(uint64_t)/1]; };
 
 union  int16_u { int16_t  int16; int8_t   int8[ sizeof(int16_t)/1]; };
 union  int32_u { int32_t  int32; int16_t  int16[sizeof(int32_t)/2]; int8_t  int8[ sizeof(int32_t)/1]; };
-union  int64_u { int64_t  int64; int32_t  int32[sizeof(int64_t)/4]; int16_t int16[sizeof(int64_t)/2]; int8_t int8[sizeof(int32_t)/1]; };
+union  int64_u { int64_t  int64; int32_t  int32[sizeof(int64_t)/4]; int16_t int16[sizeof(int64_t)/2]; int8_t int8[sizeof(int64_t)/1]; };
 
 
 // ----------------------------------------------------------------------------

The current implementation of neo430_bswap seems to be buggy. In my case, the compiler selected a totally unrelated register to call swpb on (not the one containing a), which obviously caused the rest of the program to fail.

I'm also confused why swpb is called with two operands, since the instruction seems to have only one...

This code seems to work:

uint16_t neo430_bswap(uint16_t a) {

  register uint16_t r = a;
  asm ("swpb %0" : "+r" (r));
  return r;
}

Note, that I also dropped the volatile qualifier because the ASM code is "pure" (i.e. the outputs depend only on inputs). I would also recommend to move the function to the header and mark it as inline.

In the neo430 Xmen .vhd , we knows 1x16bit splite to 2x8bit , but why the WEbit is 2bit ?
I see the RTL, Xmem's R/W_ADDR was connect to addr_i [9:1] , I donot understand it .....

RTL/ Xmem.vhd :
acc_en <= '1' when (addr_i >= imem_base_c) and (addr_i < std_ulogic_vector(unsigned(imem_base_c) + IMEM_SIZE)) else '0';
addr <= to_integer(unsigned(addr_i(index_size_f(IMEM_SIZE/2) downto 1))); -- word aligned

i want to use 2pcs 8bit eeprom and 2pcs 8bit sram replace the imem and dmem ,
when i use 2x8bit memory , i splite the data[15:0] to data[15:8] and data[7:0] , only 1 WEbit , can it works ?
i found the ice40up Xmem.vhd :

spram_we <= '1' when ((acc_en and (wren_i(0) or wren_i(1))) = '1') else '0'; -- global write enable
spram_be(1 downto 0) <= "11" when (wren_i(0) = '1') else "00"; -- low byte write enable
spram_be(3 downto 2) <= "11" when (wren_i(1) = '1') else "00"; -- high byte write enable

does it means every clk only to do 1 mission : only read / write low byte / write high byte / write a word ?
so ........for mychip( clk, addr, dout, din , we ) ---> it need to writing like these ?
mymem_clk <= std_logic(clk_i);
mymem_addr <= std_logic_vector(addr_i(13+1 downto 0+1)); -- addr /2
mymem_din <= std_logic_vector(data_i(15 downto 0));
rdata <= std_ulogic_vector(mymem_dout );
mymem_we_low <=std_logic( wren_i(0) );
mymem_we_high <=std_logic( wren_i(0) );

acc_en is not need now ?
how about the 16bit flash and 16bit sdram interface ?

mymem_clk <= std_logic(clk_i);
mymem_addr <= std_logic_vector(addr_i(13+1 downto 0+1)); -- addr /2
mymem_din <= std_logic_vector(data_i(15 downto 0));
rdata <= std_ulogic_vector(mymem_dout );
mymem_we <=std_logic( wren_i(0) or wren_i(1) );

sorry for my VHDL , i just learn it yesterday ........

I'd like to extend the GPIO module so it has a TOGGLE register.

I'd like to be able to do this from c code:

#define GPIO_TOGGLE (*(REG16 0xFFB8)) // -/w: parallel toggle
...
GPIO_TOGGLE = 1 << 0; // toggles GPIO[0]
GPIO_TOGGLE = 1 << 1; // toggles GPIO[1] .. etc
GPIO_TOGGLE = (1 << 3 | 1<< 4); // toggle GPIO[3], and GPIO[4]

I started by appending a new register to the gpio base:

index ee901d0..c7efc08 100644
--- a/rtl/core/neo430_package.vhd
+++ b/rtl/core/neo430_package.vhd
@@ -101,12 +101,13 @@ package neo430_package is
 
   -- IO: GPIO  --
   constant gpio_base_c : std_ulogic_vector(15 downto 0) := x"FFB0";
-  constant gpio_size_c : natural := 8; -- bytes
+  constant gpio_size_c : natural := 10; -- bytes
 
   constant gpio_in_addr_c      : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"0000");
   constant gpio_out_addr_c     : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"0002");
   constant gpio_ctrl_addr_c    : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"0004");
   constant gpio_irqmask_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"0006");
+  constant gpio_toggle_addr_c  : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"0008");

However, I'm not sure how best to access the current GPIO PORT value and xor it with the operand provided.

Any hints ?