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STMicroelectronics customized version of OpenOCD supporting STM32 MCUs and MPUs

License: Other

Makefile 0.70% Shell 0.25% M4 0.38% Perl 2.46% C 88.66% Assembly 1.91% Python 0.64% Haskell 0.02% Tcl 2.06% GDB 0.04% HTML 2.07% Pawn 0.62% Roff 0.19% POV-Ray SDL 0.01%

openocd gdbserver debugger stm32 stm32cubeide stmicroelectronics stm32mp1 stm32mcu stm32mpu

openocd's Introduction

STMicroelectronics/OpenOCD

1. Overview

The Open On-Chip Debugger (OpenOCD) is a free software aiming to provide debugging, in-system programming and boundary-scan testing.

To be used within STM32CubeIDE, STMicroelectronics modified OpenOCD to support:

All STM32 MCU and MPU devices
All ST-Link variants and features

STMicroelectronics is actively working at merging these modifications in the official OpenOCD. In the mean time, these modifications are available in this repository.

This software component is licensed under GNU General Public License v2

For more information regarding OpenOCD please refer to:

the original README
OpenOCD website or documentation: HTML - PDF

2. Contributing guide

This part serves as a checklist before contributing to this repository.

Before opening an issue

To report a bug/request please file an issue in the right repository (example for OpenOCD). But check the following boxes before posting an issue:

Make sure you are using the latest commit (major releases are Tagged, but corrections are available as new commits).
Make sure your issue is not already reported/fixed on GitHub or discussed on a previous Issue. Don't forget to browse into the Closed Issues.

Pull Requests

For the moment, the Pull Request feature is not deployed. STMicroelectronics is working on a Contributor License Agreement procedure

openocd's People

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openocd's Issues

STM32WL error flashing with enabled LoRa middleware using OpenOCD

Hello everyone,

I have an Olimex BB-SMT32WL that is based on a STM32WLE5CCU6. I use STM32CubeIDE and opened a new project for exactly the STM32WLE5CCU6.

Firmware Package Name and Version STM32Cube FW_WL V1.3.0

If I just configure like a GPIO Output to High it compiles and I can succesfully flash and debug it using STM32CubeIDE and openocd gdb running via terminal.

But as soon as I open the .ioc and simply enable SubGHZ and LoRaWAN things stop working, while it still compiles it won't flash anymore, throwing me this error:

(I also tried Arduino STM32duino but I'm getting the same error..)

Open On-Chip Debugger 0.12.0-00024-gc3ff39f8b (2023-06-26-16:51) [https://github.com/STMicroelectronics/OpenOCD]

Licensed under GNU GPL v2

For bug reports, read

        http://openocd.org/doc/doxygen/bugs.html

swd

adapter speed: 1000 kHz

 

stm32wlx_cti_prepare_restart_one

Info : Listening on port 6666 for tcl connections

Info : Listening on port 4444 for telnet connections

Info : CMSIS-DAP: SWD supported

Info : CMSIS-DAP: FW Version = 1.0

Info : CMSIS-DAP: Interface Initialised (SWD)

Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 0 TDO = 0 nTRST = 0 nRESET = 1

Info : CMSIS-DAP: Interface ready

Info : clock speed 4000 kHz

Info : SWD DPIDR 0x6ba02477

Info : [stm32wlx.cm4] Cortex-M4 r0p1 processor detected

Info : [stm32wlx.cm4] target has 6 breakpoints, 4 watchpoints

Info : starting gdb server for stm32wlx.cm4 on 3333

Info : Listening on port 3333 for gdb connections

Info : accepting 'gdb' connection on tcp/3333

Info : device idcode = 0x10016497 (STM32WLE/WL5x - Rev 'unknown' : 0x1001)

Info : RDP level 0 (0xAA)

Info : flash size = 256 KiB

Info : flash mode : single-bank

undefined debug reason 8 - target needs reset

[stm32wlx.cm4] halted due to debug-request, current mode: Thread

xPSR: 0x01000000 pc: 0x1fff2b6c msp: 0x20001508

Info : Padding image section 0 at 0x0800f894 with 4 bytes (bank write end alignment)

Info : SWD DPIDR 0x6ba02477

Error: Failed to write memory at 0x20009ff8

Error: block write failed

Error: error writing to flash at address 0x08000000 at offset 0x00000000

Warn : keep_alive() was not invoked in the 1000 ms timelimit. GDB alive packet not sent! (6795 ms). Workaround: increase "set remotetimeout" in GDB

[stm32wlx.cm4] halted due to debug-request, current mode: Thread

xPSR: 0x01000000 pc: 0x1fff2b6c msp: 0x20001508

shutdown command invoked

Info : dropped 'gdb' connection

Thanks in advance

Build fails on raspberry pi 4

Describe the bug
Compilation throws

libtool: compile:  gcc -DHAVE_CONFIG_H -I. -I./src -I./src -I./src/helper -DPKGDATADIR=\"/usr/local/share/openocd\" -DBINDIR=\"/usr/local/bin\" -I./jimtcl -I./jimtcl -Wall -Wstrict-prototypes -Wformat-security -Wshadow -Wextra -Wno-unused-parameter -Wbad-function-cast -Wcast-align -Wredundant-decls -Werror -g -O2 -MT src/flash/mflash.lo -MD -MP -MF src/flash/.deps/mflash.Tpo -c src/flash/mflash.c -o src/flash/mflash.o
In file included from /usr/include/string.h:495,
                 from ./src/helper/system.h:27,
                 from ./config.h:338,
                 from src/flash/mflash.c:19:
In function ‘memset’,
    inlined from ‘mg_gen_ataid’ at src/flash/mflash.c:1162:2,
    inlined from ‘mg_storage_config’ at src/flash/mflash.c:1174:2:
/usr/include/aarch64-linux-gnu/bits/string_fortified.h:71:10: error: ‘__builtin_memset’ offset [509, 512] from the object at ‘buff’ is out of the bounds of referenced subobject ‘reserved7’ with type ‘mg_io_uint8[186]’ {aka ‘unsigned char[186]’} at offset 322 [-Werror=array-bounds]
   71 |   return __builtin___memset_chk (__dest, __ch, __len, __bos0 (__dest));
      |

How To Reproduce

Clean install Ubuntu 20.04 on Raspberry pi 4 (4gb)
Install libusb and clone this repo.

sudo apt install libusb-1.0-0 libusb-1.0-0-dev
git clone --recursive https://github.com/STMicroelectronics/OpenOCD.git
cd OpenOCD

Try to build

./bootstrap
./configure
make

Also tried with:

./configure --enable-sysfsgpio --enable-bcm2835gpio

Additional Context
Raspberry pi support would be very handy. Please let me know if I am doing anything wrong.

Out of bound error

In src/flash/mflash.h the line

mg_io_uint8 reserved7[186];

should be changed to

mg_io_uint8 reserved7[190];

This is obviously an error, since in mflash.c reserved7 is accessed using
memset(pSegIdDrvInfo->reserved7, 0x00, 190);

Current gcc compiler flags this with an out of bound warning. In combination with the "Werror" flag, the compilation will be aborted.

This repository seems to be out of date

I am having trouble using openocd gdb server remotely with STM32CubeIDE. I can not build a matching version, because this repository appears to be behind the shipping version.
Please update this repository.

This is the version that is shipped with it STM32CubeIDE:

Open On-Chip Debugger 0.11.0+dev-00449-g53fa0f7 (2022-06-09-09:45) [https://github.com/STMicroelectronics/OpenOCD]
Licensed under GNU GPL v2

‘misc_items’ may be used uninitialized in stlink_usb.c/stlink_dap_op_queue_run_interna

I've already created a pull request about this issue (#13) which has been closed automatically because I need to sign a contributors agreement.
Because this doesn't justify the effort for me, I've created this issue.

Examination of CM4 core on STM32H747XIH fails

Hello,
I'm unable to debug the CM4 core on a development board with the dual-core STM32H747XIH via SWD and a CMSIS-DAP probe using the most recent openocd-cubeide-r5 branch (as well as with current upstream OpenOCD).
Examination of the core always fails with Cortex-M PARTNO 0x0 is unrecognized. Debugging code running on the CM7 core (with DUAL_CORE set to 0), as well as writing flash, works without issues.

Here's the OpenOCD config I'm using:

source [find interface/cmsis-dap.cfg]
transport select swd
set DUAL_CORE 1
source [find target/stm32h7x_dual_bank.cfg]
init
reset init

And this is the corresponding output:

Open On-Chip Debugger 0.12.0-rc1+dev-00061-ga79285f2f (2023-04-09-18:01) [https://github.com/STMicroelectronics/OpenOCD]
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
Info : Using CMSIS-DAPv2 interface with VID:PID=0x2e8a:0x000c, serial=E660C062134B2035
Info : CMSIS-DAP: SWD supported
Info : CMSIS-DAP: Atomic commands supported
Info : CMSIS-DAP: Test domain timer supported
Info : CMSIS-DAP: FW Version = 2.0.0
Info : CMSIS-DAP: Interface Initialised (SWD)
Info : SWCLK/TCK = 0 SWDIO/TMS = 0 TDI = 0 TDO = 0 nTRST = 0 nRESET = 0
Info : CMSIS-DAP: Interface ready
Info : clock speed 10000 kHz
Info : SWD DPIDR 0x6ba02477
Info : [stm32h7x.cpu0] Cortex-M7 r1p1 processor detected
Info : [stm32h7x.cpu0] target has 8 breakpoints, 4 watchpoints
Error: [stm32h7x.cpu1] Cortex-M PARTNO 0x0 is unrecognized
Warn : target stm32h7x.cpu1 examination failed
Info : gdb port disabled
Info : starting gdb server for stm32h7x.cpu0 on 3333
Info : Listening on port 3333 for gdb connections
Info : starting gdb server for stm32h7x.cpu1 on 3334
Info : Listening on port 3334 for gdb connections
Error: [stm32h7x.cpu1] Cortex-M PARTNO 0x0 is unrecognized
[stm32h7x.cpu0] halted due to debug-request, current mode: Thread 
xPSR: 0x01000000 pc: 0x08008728 msp: 0x20020000
Error: [stm32h7x.cpu1] Cortex-M PARTNO 0x0 is unrecognized
TARGET: stm32h7x.cpu1 - Not examined

Failed to read memory

Failed to read memory at 0x080f6004

This happen when I try execute a read command using flash read_bank.

Target: stm32wbx
Interface: raspberrypi2-native (SWD)

If I use the same command, but with st-link as interface, it works

Unable to use with Nucleo-H753ZI board

Issue

Unable to use Nucleo-H753ZI board with OpenOCD.

The OpenOCD fails to halt the µCU, fails to erase it as well.

Error: timed out while waiting for target halted
Error executing event gdb-attach on target STM32H753ZITx.cm7:
TARGET: STM32H753ZITx.cm7 - Not halted
Info : New GDB Connection: 2, Target STM32H753ZITx.cm7, state: running
Warn : GDB connection 2 on target STM32H753ZITx.cm7 not halted
Error: timed out while waiting for target halted
Error executing event gdb-flash-erase-start on target STM32H753ZITx.cm7:
TARGET: STM32H753ZITx.cm7 - Not halted
Error: failed erasing sectors 0 to 2
Error: flash_erase returned -304

See the "Outputs" for more details.

Environment

Board

Nucleo-753ZI with the onboard programmer.

Windows 10

Version: 10.0.19042 Build 19042

STLink-V3

Versions:

V3J8M3
V3J9M3 (latest)

STM32CubeIDE

Version: 1.8.0
Build: 11526_20211125_0815 (UTC)

OpenOCD

Tried several versions and bundles

STM32CubeIDE Plugin

Versions:

Open On-Chip Debugger 0.11.0-rc2+dev-00044-g8340bb0 (2021-06-02-17:29)
Open On-Chip Debugger 0.11.0+dev-00438-ga75fc63 (2021-11-03-15:27) (latest)

xPack OpenOCD

Version: 0.11.0-2 (win32-x64)

Official

Version: 0.11.0

Generated OpenOCD Config File

STM32CubeIDE Debug_OpenOCD.cfg

# Generated by STM32CubeIDE
# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)

source [find interface/stlink-dap.cfg]


set WORKAREASIZE 0x8000

transport select "dapdirect_swd"

set CHIPNAME STM32H753ZITx
set BOARDNAME NUCLEO-H753ZI

# Enable debug when in low power modes
set ENABLE_LOW_POWER 1

# Stop Watchdog counters when halt
set STOP_WATCHDOG 1

# STlink Debug clock frequency
set CLOCK_FREQ 8000

# Reset configuration
# use hardware reset, connect under reset
# connect_assert_srst needed if low power mode application running (WFI...)
reset_config srst_only srst_nogate connect_assert_srst
set CONNECT_UNDER_RESET 1
set CORE_RESET 0

# ACCESS PORT NUMBER
set AP_NUM 0
# GDB PORT
set GDB_PORT 3333

set DUAL_BANK 1


# BCTM CPU variables

source [find target/stm32h7x.cfg]

Outputs

OpenOCD (STM32CubeIDE Plugin)

Debug Level 3

0.11.0+dev-00438-ga75fc63 (2021-11-03-15:27)

Open On-Chip Debugger 0.11.0+dev-00438-ga75fc63 (2021-11-03-15:27)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
stm32h7x_cti_prepare_restart_one
User : 5 27 options.c:63 configuration_output_handler(): debug_level: 3
User : 6 28 options.c:63 configuration_output_handler(): 
Debug: 7 28 command.c:201 script_debug(): command - gdb_report_data_abort enable
Debug: 8 28 command.c:201 script_debug(): command - gdb_port 3333
Debug: 9 29 command.c:201 script_debug(): command - tcl_port 6666
Debug: 10 29 command.c:201 script_debug(): command - telnet_port 4444
Info : 11 31 server.c:312 add_service(): Listening on port 6666 for tcl connections
Info : 12 31 server.c:312 add_service(): Listening on port 4444 for telnet connections
Debug: 13 32 command.c:201 script_debug(): command - init
Debug: 14 32 command.c:201 script_debug(): command - target init
Debug: 15 32 command.c:201 script_debug(): command - target names
Debug: 16 33 command.c:201 script_debug(): command - STM32H753ZITx.ap2 cget -event gdb-flash-erase-start
Debug: 17 33 command.c:201 script_debug(): command - STM32H753ZITx.ap2 configure -event gdb-flash-erase-start reset init
Debug: 18 34 command.c:201 script_debug(): command - STM32H753ZITx.ap2 cget -event gdb-flash-write-end
Debug: 19 34 command.c:201 script_debug(): command - STM32H753ZITx.ap2 configure -event gdb-flash-write-end reset halt
Debug: 20 35 command.c:201 script_debug(): command - STM32H753ZITx.ap2 cget -event gdb-attach
Debug: 21 35 command.c:201 script_debug(): command - STM32H753ZITx.ap2 configure -event gdb-attach halt 1000
Debug: 22 36 command.c:201 script_debug(): command - STM32H753ZITx.cm7 cget -event gdb-flash-erase-start
Debug: 23 36 command.c:201 script_debug(): command - STM32H753ZITx.cm7 configure -event gdb-flash-erase-start reset init
Debug: 24 37 command.c:201 script_debug(): command - STM32H753ZITx.cm7 cget -event gdb-flash-write-end
Debug: 25 37 command.c:201 script_debug(): command - STM32H753ZITx.cm7 configure -event gdb-flash-write-end reset halt
Debug: 26 38 command.c:201 script_debug(): command - STM32H753ZITx.cm7 cget -event gdb-attach
Debug: 27 38 target.c:1650 handle_target_init_command(): Initializing targets...
Debug: 28 38 mem_ap.c:69 mem_ap_init_target(): mem_ap_init_target
Debug: 29 39 semihosting_common.c:99 semihosting_common_init():  
Debug: 30 39 stlink_usb.c:5121 stlink_dap_init(): stlink_dap_init()
Debug: 31 40 stlink_usb.c:3682 stlink_open(): stlink_open
Debug: 32 40 stlink_usb.c:3696 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3748 serial: 
Debug: 33 40 stlink_usb.c:3696 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374b serial: 
Debug: 34 41 stlink_usb.c:3696 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374d serial: 
Debug: 35 41 stlink_usb.c:3696 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374e serial: 
Debug: 36 41 stlink_usb.c:3696 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374f serial: 
Debug: 37 42 stlink_usb.c:3696 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3752 serial: 
Debug: 38 42 stlink_usb.c:3696 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3753 serial: 
Debug: 39 43 stlink_usb.c:3696 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3754 serial: 
Debug: 40 43 stlink_usb.c:3696 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3755 serial: 
Debug: 41 44 stlink_usb.c:3696 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3757 serial: 
Info : 42 311 stlink_usb.c:1432 stlink_usb_version(): STLINK V3J9M3 (API v3) VID:PID 0483:374E
Debug: 43 312 stlink_usb.c:1653 stlink_usb_exit_mode(): MODE: 0x01
Info : 44 312 stlink_usb.c:1464 stlink_usb_check_voltage(): Target voltage: 3.282869
Debug: 45 313 stlink_usb.c:1721 stlink_usb_init_mode(): MODE: 0x01
Debug: 46 313 stlink_usb.c:3087 stlink_dump_speed_map(): Supported clock speeds are:
Debug: 47 314 stlink_usb.c:3090 stlink_dump_speed_map(): 24000 kHz
Debug: 48 314 stlink_usb.c:3090 stlink_dump_speed_map(): 8000 kHz
Debug: 49 314 stlink_usb.c:3090 stlink_dump_speed_map(): 3300 kHz
Debug: 50 315 stlink_usb.c:3090 stlink_dump_speed_map(): 1000 kHz
Debug: 51 315 stlink_usb.c:3090 stlink_dump_speed_map(): 200 kHz
Debug: 52 315 stlink_usb.c:3090 stlink_dump_speed_map(): 50 kHz
Debug: 53 315 stlink_usb.c:3090 stlink_dump_speed_map(): 5 kHz
Debug: 54 429 stlink_usb.c:1781 stlink_usb_init_mode(): MODE: 0x02
Debug: 55 449 stlink_usb.c:4072 stlink_usb_open_ap(): AP 0 enabled
Debug: 56 481 stlink_usb.c:3770 stlink_open(): Using TAR autoincrement: 1024
Debug: 57 482 core.c:1779 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 58 482 core.c:1783 adapter_khz_to_speed(): have interface set up
Debug: 59 485 core.c:1779 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 60 485 core.c:1783 adapter_khz_to_speed(): have interface set up
Info : 61 486 core.c:1559 adapter_init(): clock speed 8000 kHz
Debug: 62 487 openocd.c:143 handle_init_command(): Debug Adapter init complete
Debug: 63 487 command.c:201 script_debug(): command - transport init
Debug: 64 488 transport.c:230 handle_transport_init(): handle_transport_init
Debug: 65 489 adi_v5_dapdirect.c:184 dapdirect_init(): dapdirect_init()
Debug: 66 489 stlink_usb.c:5167 stlink_dap_reset(): stlink_dap_reset(1)
Debug: 67 490 core.c:639 adapter_system_reset(): SRST line asserted
Debug: 68 490 command.c:201 script_debug(): command - dap init
Debug: 69 491 arm_dap.c:107 dap_init_all(): Initializing all DAPs ...
Info : 70 491 stlink_usb.c:4142 stlink_dap_op_connect(): stlink_dap_op_connect(connect)
Debug: 71 492 arm_adi_v5.c:670 dap_dp_init(): STM32H753ZITx.dap
Debug: 72 492 arm_adi_v5.c:702 dap_dp_init(): DAP: wait CDBGPWRUPACK
Debug: 73 492 arm_adi_v5.h:546 dap_dp_poll_register(): DAP: poll 4, mask 0x20000000, value 0x20000000
Debug: 74 495 arm_adi_v5.c:710 dap_dp_init(): DAP: wait CSYSPWRUPACK
Debug: 75 495 arm_adi_v5.h:546 dap_dp_poll_register(): DAP: poll 4, mask 0x80000000, value 0x80000000
Debug: 76 499 stlink_usb.c:2014 stlink_usb_idcode(): IDCODE: 0x6BA02477
Info : 77 499 stlink_usb.c:4171 stlink_dap_op_connect(): SWD DPIDR 0x6ba02477
Debug: 78 499 openocd.c:160 handle_init_command(): Examining targets...
Debug: 79 500 target.c:1838 target_call_event_callbacks(): target event 19 (examine-start) for core STM32H753ZITx.ap2
Debug: 80 500 stlink_usb.c:4072 stlink_usb_open_ap(): AP 2 enabled
Debug: 81 503 arm_adi_v5.c:817 mem_ap_init(): MEM_AP Packed Transfers: disabled
Debug: 82 504 arm_adi_v5.c:828 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0
Debug: 83 504 target.c:1838 target_call_event_callbacks(): target event 21 (examine-end) for core STM32H753ZITx.ap2
Debug: 84 505 target.c:1838 target_call_event_callbacks(): target event 19 (examine-start) for core STM32H753ZITx.cm7
Debug: 85 509 arm_adi_v5.c:817 mem_ap_init(): MEM_AP Packed Transfers: disabled
Debug: 86 509 arm_adi_v5.c:828 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0
Debug: 87 511 target.c:2617 target_read_u32(): address: 0xe000ed00, value: 0x411fc271
Info : 88 512 cortex_m.c:2089 cortex_m_examine(): STM32H753ZITx.cm7: Cortex-M7 r1p1 processor detected
Debug: 89 512 cortex_m.c:2101 cortex_m_examine(): cpuid: 0x411fc271
Debug: 90 514 target.c:2617 target_read_u32(): address: 0xe000ef40, value: 0x10110221
Debug: 91 518 target.c:2617 target_read_u32(): address: 0xe000ef44, value: 0x12000011
Debug: 92 518 cortex_m.c:2121 cortex_m_examine(): Cortex-M7 floating point feature FPv5_DP found
Debug: 93 520 target.c:2617 target_read_u32(): address: 0xe000edf0, value: 0x01010001
Debug: 94 520 target.c:2705 target_write_u32(): address: 0xe000edfc, value: 0x01000000
Debug: 95 525 target.c:2617 target_read_u32(): address: 0xe0002000, value: 0x10000081
Debug: 96 525 target.c:2705 target_write_u32(): address: 0xe0002008, value: 0x00000000
Debug: 97 527 target.c:2705 target_write_u32(): address: 0xe000200c, value: 0x00000000
Debug: 98 528 target.c:2705 target_write_u32(): address: 0xe0002010, value: 0x00000000
Debug: 99 529 target.c:2705 target_write_u32(): address: 0xe0002014, value: 0x00000000
Debug: 100 530 target.c:2705 target_write_u32(): address: 0xe0002018, value: 0x00000000
Debug: 101 531 target.c:2705 target_write_u32(): address: 0xe000201c, value: 0x00000000
Debug: 102 532 target.c:2705 target_write_u32(): address: 0xe0002020, value: 0x00000000
Debug: 103 534 target.c:2705 target_write_u32(): address: 0xe0002024, value: 0x00000000
Debug: 104 535 cortex_m.c:2192 cortex_m_examine(): FPB fpcr 0x10000081, numcode 8, numlit 0
Debug: 105 536 target.c:2617 target_read_u32(): address: 0xe0001000, value: 0x40000000
Debug: 106 536 cortex_m.c:1924 cortex_m_dwt_setup(): DWT_CTRL: 0x40000000
Debug: 107 538 target.c:2617 target_read_u32(): address: 0xe0001fbc, value: 0x00000000
Debug: 108 538 cortex_m.c:1931 cortex_m_dwt_setup(): DWT_DEVARCH: 0x0
Debug: 109 539 target.c:2705 target_write_u32(): address: 0xe0001028, value: 0x00000000
Debug: 110 542 target.c:2705 target_write_u32(): address: 0xe0001038, value: 0x00000000
Debug: 111 544 target.c:2705 target_write_u32(): address: 0xe0001048, value: 0x00000000
Debug: 112 545 target.c:2705 target_write_u32(): address: 0xe0001058, value: 0x00000000
Debug: 113 546 cortex_m.c:1980 cortex_m_dwt_setup(): DWT dwtcr 0x40000000, comp 4, watch/trigger
Info : 114 547 cortex_m.c:2202 cortex_m_examine(): STM32H753ZITx.cm7: target has 8 breakpoints, 4 watchpoints
Debug: 115 547 target.c:1838 target_call_event_callbacks(): target event 21 (examine-end) for core STM32H753ZITx.cm7
Debug: 116 548 target.c:4817 target_handle_event(): target(1): STM32H753ZITx.cm7 (cortex_m) event: 21 (examine-end) action: 
		global _CHIPNAME
		global $_CHIPNAME.USE_CTI

		if { ![using_hla] } {
			# Disable corresponding CTI by default
			stm32h7x_cti_stop_one cm7_cti
		
			stm32h7x_dbgmcu_init
		}

		if { [set $_CHIPNAME.USE_CTI] } {
			stm32h7x_cti_start_cm7_cti
		}
	
Debug: 117 549 command.c:201 script_debug(): command - transport select
Debug: 119 551 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 120 552 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti write INACK 0x01
Debug: 121 555 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti write INACK 0x00
Debug: 122 557 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti write INEN0 0
Debug: 123 559 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti write OUTEN0 0
Debug: 124 561 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti enable off
Debug: 125 562 command.c:201 script_debug(): command - transport select
Debug: 126 563 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 127 564 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 128 565 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759017988 1
Debug: 129 565 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1004; size 4; count 1
Debug: 130 566 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 131 567 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759017988 7340095
Debug: 132 569 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1004; size 4; count 1
Debug: 133 570 command.c:201 script_debug(): command - transport select
Debug: 134 570 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 135 572 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 136 573 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759017988 1
Debug: 137 574 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1004; size 4; count 1
Debug: 138 575 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 139 577 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759017988 7340095
Debug: 140 578 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1004; size 4; count 1
Debug: 141 579 command.c:201 script_debug(): command - transport select
Debug: 142 580 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 143 581 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 144 582 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759017988 1
Debug: 145 583 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1004; size 4; count 1
Debug: 146 584 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 147 585 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759017988 7340095
Debug: 148 586 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1004; size 4; count 1
Debug: 149 587 command.c:201 script_debug(): command - transport select
Debug: 150 589 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 151 590 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 152 591 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759018036 1
Debug: 153 592 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1034; size 4; count 1
Debug: 154 593 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 155 594 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759018036 64
Debug: 156 597 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1034; size 4; count 1
Debug: 157 598 command.c:201 script_debug(): command - transport select
Debug: 158 598 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 159 600 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 160 601 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759018044 1
Debug: 161 602 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e103c; size 4; count 1
Debug: 162 604 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 163 606 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759018044 2048
Debug: 164 607 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e103c; size 4; count 1
Debug: 165 608 command.c:201 script_debug(): command - transport select
Debug: 166 609 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 167 611 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 168 612 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759018068 1
Debug: 169 613 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1054; size 4; count 1
Debug: 170 615 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 171 616 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759018068 786432
Debug: 172 617 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1054; size 4; count 1
Debug: 173 618 command.c:201 script_debug(): command - transport select
Debug: 174 619 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 175 620 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 176 620 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759017988 1
Debug: 177 622 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1004; size 4; count 1
Debug: 178 624 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 179 624 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759017988 7340095
Debug: 180 626 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1004; size 4; count 1
Debug: 181 626 command.c:201 script_debug(): command - flash init
Debug: 182 628 tcl.c:1387 handle_flash_init_command(): Initializing flash devices...
Debug: 183 628 command.c:201 script_debug(): command - nand init
Debug: 184 628 tcl.c:498 handle_nand_init_command(): Initializing NAND devices...
Debug: 185 629 command.c:201 script_debug(): command - pld init
Debug: 186 630 pld.c:206 handle_pld_init_command(): Initializing PLDs...
Debug: 187 630 command.c:201 script_debug(): command - tpiu init
Info : 188 631 gdb_server.c:3578 gdb_target_add_one(): gdb port disabled
Info : 189 631 gdb_server.c:3539 gdb_target_start(): starting gdb server for STM32H753ZITx.cm7 on 3333
Info : 190 632 server.c:312 add_service(): Listening on port 3333 for gdb connections
Info : 191 2405 server.c:101 add_connection(): accepting 'gdb' connection on tcp/3333
Debug: 192 2407 breakpoints.c:381 breakpoint_clear_target_internal(): Delete all breakpoints for target: STM32H753ZITx.cm7
Debug: 193 2407 breakpoints.c:569 watchpoint_clear_target(): Delete all watchpoints for target: STM32H753ZITx.cm7
Debug: 194 2408 target.c:1838 target_call_event_callbacks(): target event 22 (gdb-attach) for core STM32H753ZITx.cm7
Debug: 195 2408 target.c:4817 target_handle_event(): target(1): STM32H753ZITx.cm7 (cortex_m) event: 22 (gdb-attach) action: 
		global _CONNECT_UNDER_RESET

		# Needed to be able to use the connect_assert_srst in reset_config
		if { $_CONNECT_UNDER_RESET == 1 } {
			reset init
		} else {
			if { [set $_CHIPNAME.DUAL_CORE] } {
				soft_reset_halt
			}
		}
	
Debug: 196 2410 command.c:201 script_debug(): command - reset init
Debug: 197 2412 target.c:1856 target_call_reset_callbacks(): target reset 3 (init)
Debug: 198 2412 target.c:1856 target_call_reset_callbacks(): target reset 3 (init)
Debug: 199 2412 command.c:201 script_debug(): command - expr [catch {ocd_process_reset_inner $MODE} result] == 0
Debug: 200 2413 command.c:201 script_debug(): command - target names
Debug: 201 2413 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event reset-start
Debug: 202 2414 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event reset-start
Debug: 203 2414 command.c:201 script_debug(): command - transport select
Debug: 204 2415 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 205 2415 command.c:201 script_debug(): command - transport select
Debug: 206 2415 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 207 2416 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event examine-start
Debug: 208 2416 command.c:201 script_debug(): command - STM32H753ZITx.ap2 arp_examine allow-defer
Debug: 209 2417 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event examine-end
Debug: 210 2417 command.c:201 script_debug(): command - transport select
Debug: 211 2417 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 212 2418 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event examine-start
Debug: 213 2418 command.c:201 script_debug(): command - STM32H753ZITx.cm7 arp_examine allow-defer
Debug: 214 2421 arm_adi_v5.c:817 mem_ap_init(): MEM_AP Packed Transfers: disabled
Debug: 215 2421 arm_adi_v5.c:828 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0
Debug: 216 2422 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event examine-end
Debug: 217 2422 target.c:4817 target_handle_event(): target(1): STM32H753ZITx.cm7 (cortex_m) event: 21 (examine-end) action: 
		global _CHIPNAME
		global $_CHIPNAME.USE_CTI

		if { ![using_hla] } {
			# Disable corresponding CTI by default
			stm32h7x_cti_stop_one cm7_cti
		
			stm32h7x_dbgmcu_init
		}

		if { [set $_CHIPNAME.USE_CTI] } {
			stm32h7x_cti_start_cm7_cti
		}
	
Debug: 218 2424 command.c:201 script_debug(): command - transport select
Debug: 219 2424 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 220 2425 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti write INACK 0x01
Debug: 221 2426 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti write INACK 0x00
Debug: 222 2427 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti write INEN0 0
Debug: 223 2428 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti write OUTEN0 0
Debug: 224 2430 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti enable off
Debug: 225 2430 command.c:201 script_debug(): command - transport select
Debug: 226 2431 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 227 2431 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 228 2431 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759017988 1
Debug: 229 2432 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1004; size 4; count 1
Debug: 230 2433 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 231 2434 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759017988 7340095
Debug: 232 2434 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1004; size 4; count 1
Debug: 233 2435 command.c:201 script_debug(): command - transport select
Debug: 234 2436 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 235 2436 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 236 2437 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759017988 1
Debug: 237 2437 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1004; size 4; count 1
Debug: 238 2438 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 239 2439 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759017988 7340095
Debug: 240 2439 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1004; size 4; count 1
Debug: 241 2441 command.c:201 script_debug(): command - transport select
Debug: 242 2441 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 243 2442 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 244 2442 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759017988 1
Debug: 245 2443 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1004; size 4; count 1
Debug: 246 2444 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 247 2444 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759017988 7340095
Debug: 248 2445 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1004; size 4; count 1
Debug: 249 2446 command.c:201 script_debug(): command - transport select
Debug: 250 2447 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 251 2447 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 252 2447 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759018036 1
Debug: 253 2448 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1034; size 4; count 1
Debug: 254 2449 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 255 2450 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759018036 64
Debug: 256 2450 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1034; size 4; count 1
Debug: 257 2451 command.c:201 script_debug(): command - transport select
Debug: 258 2452 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 259 2453 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 260 2453 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759018044 1
Debug: 261 2453 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e103c; size 4; count 1
Debug: 262 2454 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 263 2455 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759018044 2048
Debug: 264 2456 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e103c; size 4; count 1
Debug: 265 2458 command.c:201 script_debug(): command - transport select
Debug: 266 2459 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 267 2459 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 268 2460 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759018068 1
Debug: 269 2460 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1054; size 4; count 1
Debug: 270 2462 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 271 2462 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759018068 786432
Debug: 272 2463 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1054; size 4; count 1
Debug: 273 2466 command.c:201 script_debug(): command - transport select
Debug: 274 2466 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 275 2467 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 276 2468 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759017988 1
Debug: 277 2468 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1004; size 4; count 1
Debug: 278 2471 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 279 2472 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759017988 7340095
Debug: 280 2472 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1004; size 4; count 1
Debug: 281 2474 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event reset-assert-pre
Debug: 282 2474 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event reset-assert-pre
Debug: 283 2475 command.c:201 script_debug(): command - transport select
Debug: 284 2475 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 285 2476 command.c:201 script_debug(): command - STM32H753ZITx.ap2 arp_reset assert 1
Debug: 286 2477 target.c:2194 target_free_all_working_areas_restore(): freeing all working areas
Debug: 287 2477 mem_ap.c:133 mem_ap_assert_reset(): mem_ap_assert_reset
Debug: 288 2478 command.c:201 script_debug(): command - transport select
Debug: 289 2478 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 290 2478 command.c:201 script_debug(): command - STM32H753ZITx.cm7 arp_reset assert 1
Debug: 291 2479 target.c:2194 target_free_all_working_areas_restore(): freeing all working areas
Debug: 292 2479 cortex_m.c:1162 cortex_m_assert_reset(): target->state: running
Debug: 293 2559 cortex_m.c:742 cortex_m_halt(): target->state: reset
Debug: 294 2559 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event reset-assert-post
Debug: 295 2560 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event reset-assert-post
Debug: 296 2560 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event reset-deassert-pre
Debug: 297 2561 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event reset-deassert-pre
Debug: 298 2561 command.c:201 script_debug(): command - transport select
Debug: 299 2561 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 300 2562 command.c:201 script_debug(): command - STM32H753ZITx.ap2 arp_reset deassert 1
Debug: 301 2562 target.c:2194 target_free_all_working_areas_restore(): freeing all working areas
Debug: 302 2563 target.c:1838 target_call_event_callbacks(): target event 0 (gdb-halt) for core STM32H753ZITx.ap2
Debug: 303 2563 target.c:1838 target_call_event_callbacks(): target event 1 (halted) for core STM32H753ZITx.ap2
Debug: 304 2563 mem_ap.c:86 mem_ap_arch_state(): mem_ap_arch_state
Debug: 305 2564 mem_ap.c:163 mem_ap_deassert_reset(): mem_ap_deassert_reset
Debug: 306 2564 command.c:201 script_debug(): command - transport select
Debug: 307 2564 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 308 2565 command.c:201 script_debug(): command - STM32H753ZITx.cm7 arp_reset deassert 1
Debug: 309 2565 target.c:2194 target_free_all_working_areas_restore(): freeing all working areas
Debug: 310 2565 cortex_m.c:1313 cortex_m_deassert_reset(): target->state: reset
Debug: 311 2566 stlink_usb.c:5167 stlink_dap_reset(): stlink_dap_reset(0)
Debug: 312 2566 core.c:643 adapter_system_reset(): SRST line released
Debug: 313 2732 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event reset-deassert-post
Debug: 314 2732 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event reset-deassert-post
Debug: 315 2733 command.c:201 script_debug(): command - transport select
Debug: 316 2734 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 317 2734 command.c:201 script_debug(): command - STM32H753ZITx.ap2 was_examined
Debug: 318 2734 command.c:201 script_debug(): command - STM32H753ZITx.ap2 arp_waitstate halted 1000
Debug: 319 2735 command.c:201 script_debug(): command - STM32H753ZITx.ap2 curstate
Debug: 320 2735 command.c:201 script_debug(): command - transport select
Debug: 321 2736 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 322 2736 command.c:201 script_debug(): command - STM32H753ZITx.cm7 was_examined
Debug: 323 2737 command.c:201 script_debug(): command - STM32H753ZITx.cm7 arp_waitstate halted 1000
Debug: 324 2738 cortex_m.c:681 cortex_m_poll(): Exit from reset with dcb_dhcsr 0x1010001
Debug: 325 2740 cortex_m.c:361 cortex_m_endreset_event(): DCB_DEMCR = 0x01000501
Debug: 326 2741 stlink_usb.c:4382 stlink_usb_misc_rw_segment(): Queue: 2 commands in 4 items
Debug: 327 2742 target.c:2705 target_write_u32(): address: 0xe0002000, value: 0x00000003
Debug: 328 2743 stlink_usb.c:4382 stlink_usb_misc_rw_segment(): Queue: 2 commands in 5 items
Debug: 329 2745 target.c:2617 target_read_u32(): address: 0xe0002000, value: 0x10000081
Debug: 330 2745 target.c:2705 target_write_u32(): address: 0xe0002008, value: 0x00000000
Debug: 331 2746 target.c:2705 target_write_u32(): address: 0xe000200c, value: 0x00000000
Debug: 332 2748 target.c:2705 target_write_u32(): address: 0xe0002010, value: 0x00000000
Debug: 333 2749 target.c:2705 target_write_u32(): address: 0xe0002014, value: 0x00000000
Debug: 334 2750 target.c:2705 target_write_u32(): address: 0xe0002018, value: 0x00000000
Debug: 335 2751 target.c:2705 target_write_u32(): address: 0xe000201c, value: 0x00000000
Debug: 336 2751 target.c:2705 target_write_u32(): address: 0xe0002020, value: 0x00000000
Debug: 337 2752 target.c:2705 target_write_u32(): address: 0xe0002024, value: 0x00000000
Debug: 338 2753 target.c:2705 target_write_u32(): address: 0xe0001020, value: 0x00000000
Debug: 339 2754 target.c:2705 target_write_u32(): address: 0xe0001024, value: 0x00000000
Debug: 340 2755 target.c:2705 target_write_u32(): address: 0xe0001028, value: 0x00000000
Debug: 341 2756 target.c:2705 target_write_u32(): address: 0xe0001030, value: 0x00000000
Debug: 342 2757 target.c:2705 target_write_u32(): address: 0xe0001034, value: 0x00000000
Debug: 343 2758 target.c:2705 target_write_u32(): address: 0xe0001038, value: 0x00000000
Debug: 344 2759 target.c:2705 target_write_u32(): address: 0xe0001040, value: 0x00000000
Debug: 345 2761 target.c:2705 target_write_u32(): address: 0xe0001044, value: 0x00000000
Debug: 346 2761 target.c:2705 target_write_u32(): address: 0xe0001048, value: 0x00000000
Debug: 347 2763 target.c:2705 target_write_u32(): address: 0xe0001050, value: 0x00000000
Debug: 348 2764 target.c:2705 target_write_u32(): address: 0xe0001054, value: 0x00000000
Debug: 349 2765 target.c:2705 target_write_u32(): address: 0xe0001058, value: 0x00000000
Debug: 350 2766 target.c:3274 target_wait_state(): waiting for target halted...
Error: 352 3767 target.c:3282 target_wait_state(): timed out while waiting for target halted
Debug: 353 3767 command.c:201 script_debug(): command - STM32H753ZITx.cm7 curstate
Debug: 355 3768 command.c:591 run_command(): Command 'reset' failed with error code -4
User : 356 3770 target.c:4842 target_handle_event(): Error executing event gdb-attach on target STM32H753ZITx.cm7:
TARGET: STM32H753ZITx.cm7 - Not halted
Debug: 357 3771 target.c:2617 target_read_u32(): address: 0x5c001000, value: 0x20036450
Debug: 358 3772 stm32h7x.c:774 stm32x_probe(): device id = 0x20036450
Info : 359 3772 stm32h7x.c:786 stm32x_probe(): Device: STM32H74x/75x
Debug: 360 3772 stm32h7x.c:798 stm32x_probe(): flash_regs_base: 0x52002000
Debug: 361 3773 target.c:2641 target_read_u16(): address: 0x1ff1e880, value: 0x0800
Info : 362 3773 stm32h7x.c:813 stm32x_probe(): flash size probed value 2048k
Info : 363 3774 stm32h7x.c:843 stm32x_probe(): STM32H7 flash has dual banks
Info : 364 3774 stm32h7x.c:864 stm32x_probe(): Bank (0) size is 1024 kb, base address is 0x08000000
Debug: 365 3775 target.c:2617 target_read_u32(): address: 0x5c001000, value: 0x20036450
Debug: 366 3776 stm32h7x.c:774 stm32x_probe(): device id = 0x20036450
Info : 367 3776 stm32h7x.c:786 stm32x_probe(): Device: STM32H74x/75x
Debug: 368 3776 stm32h7x.c:798 stm32x_probe(): flash_regs_base: 0x52002100
Debug: 369 3777 target.c:2641 target_read_u16(): address: 0x1ff1e880, value: 0x0800
Info : 370 3778 stm32h7x.c:813 stm32x_probe(): flash size probed value 2048k
Info : 371 3778 stm32h7x.c:843 stm32x_probe(): STM32H7 flash has dual banks
Info : 372 3778 stm32h7x.c:864 stm32x_probe(): Bank (1) size is 1024 kb, base address is 0x08100000
Info : 373 3779 gdb_server.c:1047 gdb_new_connection(): New GDB Connection: 1, Target STM32H753ZITx.cm7, state: running
Warn : 374 3779 gdb_server.c:1062 gdb_new_connection(): GDB connection 1 on target STM32H753ZITx.cm7 not halted
Debug: 375 3780 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qSupported:multiprocess+;swbreak+;hwbreak+;qRelocInsn+;fork-events+;vfork-events+;exec-events+;vContSupported+;QThreadEvents+;no-resumed+
Debug: 376 3780 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $PacketSize=4000;qXfer:memory-map:read+;qXfer:features:read+;qXfer:threads:read+;QStartNoAckMode+;vContSupported+#02'
Debug: 377 3782 gdb_server.c:384 gdb_log_incoming_packet(): received packet: vMustReplyEmpty
Debug: 378 3784 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $#00'
Debug: 379 3784 gdb_server.c:384 gdb_log_incoming_packet(): received packet: QStartNoAckMode
Debug: 380 3784 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $OK#9a'
Debug: 381 3785 gdb_server.c:676 gdb_get_packet_inner(): Received first acknowledgment after entering noack mode. Ignoring it.
Debug: 382 3786 gdb_server.c:384 gdb_log_incoming_packet(): received packet: !
Debug: 383 3786 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $OK#9a'
Debug: 384 3787 gdb_server.c:384 gdb_log_incoming_packet(): received packet: Hg0
Debug: 385 3787 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $OK#9a'
Debug: 386 3788 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qXfer:features:read:target.xml:0,1000
Debug: 387 3791 gdb_server.c:394 gdb_log_outgoing_packet(): sending packet: $<binary-data-3942-bytes>#d1
Debug: 388 3794 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qTStatus
Debug: 389 3794 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $#00'
Debug: 390 3795 gdb_server.c:384 gdb_log_incoming_packet(): received packet: ?
Debug: 391 3796 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $S02#b5'
Debug: 392 3797 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qXfer:threads:read::0,1000
Debug: 393 3797 gdb_server.c:394 gdb_log_outgoing_packet(): sending packet: $<binary-data-44-bytes>#02
Debug: 394 3799 gdb_server.c:384 gdb_log_incoming_packet(): received packet: Hc-1
Debug: 395 3799 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $OK#9a'
Debug: 396 3801 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qC
Debug: 397 3801 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $QC0#c4'
Debug: 398 3802 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qAttached
Debug: 399 3802 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $1#31'
Debug: 400 3804 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qOffsets
Debug: 401 3804 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $Text=0;Data=0;Bss=0#04'
Debug: 402 3805 gdb_server.c:384 gdb_log_incoming_packet(): received packet: g
Debug: 403 3806 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000#80'
Debug: 404 3809 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qXfer:memory-map:read::0,1000
Debug: 405 3809 gdb_server.c:394 gdb_log_outgoing_packet(): sending packet: $<binary-data-378-bytes>#ce
Debug: 406 3810 gdb_server.c:384 gdb_log_incoming_packet(): received packet: m8018ecc,2
Debug: 407 3810 gdb_server.c:1495 gdb_read_memory_packet(): addr: 0x0000000008018ecc, len: 0x00000002
Debug: 408 3811 target.c:2467 target_read_buffer(): reading buffer of 2 byte at 0x08018ecc
Debug: 409 3812 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $08b5#ff'
Debug: 410 3813 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qXfer:threads:read::0,1000
Debug: 411 3814 gdb_server.c:394 gdb_log_outgoing_packet(): sending packet: $<binary-data-44-bytes>#02
Debug: 412 3815 gdb_server.c:384 gdb_log_incoming_packet(): received packet: m0,4
Debug: 413 3815 gdb_server.c:1495 gdb_read_memory_packet(): addr: 0x0000000000000000, len: 0x00000004
Debug: 414 3815 target.c:2467 target_read_buffer(): reading buffer of 4 byte at 0x00000000
Debug: 415 3817 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $0696924c#d7'
Debug: 416 3819 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qSymbol::
Debug: 417 3820 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $OK#9a'
Debug: 418 3821 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qXfer:threads:read::0,1000
Debug: 419 3822 gdb_server.c:394 gdb_log_outgoing_packet(): sending packet: $<binary-data-44-bytes>#02
Debug: 420 3823 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qRcmd,57726974654450203078322030784630
Debug: 421 3833 command.c:201 script_debug(): command - target current
Debug: 422 3836 command.c:201 script_debug(): command - STM32H753ZITx.cm7 cget -dap
Debug: 423 3838 command.c:201 script_debug(): command - expr $reg_idx * 4
Debug: 424 3839 command.c:201 script_debug(): command - STM32H753ZITx.dap dpreg 8 0xF0
User : 425 3842 gdb_server.c:755 gdb_output(): O.K.
Debug: 426 3843 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $O4f2e4b2e0a#3e'
User : 427 3843 gdb_server.c:755 gdb_output(): 
Debug: 428 3843 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $O0a#e0'
Debug: 429 3844 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $OK#9a'
Debug: 430 3871 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qRcmd,52656164415020307832
Debug: 431 3873 command.c:201 script_debug(): command - target current
Debug: 432 3875 command.c:201 script_debug(): command - STM32H753ZITx.cm7 cget -ap-num
Debug: 433 3878 command.c:201 script_debug(): command - target current
Debug: 434 3885 command.c:201 script_debug(): command - STM32H753ZITx.cm7 cget -dap
Debug: 435 3888 command.c:201 script_debug(): command - expr $reg_idx * 4
Debug: 436 3891 command.c:201 script_debug(): command - expr ($reg == 8)
Debug: 437 3893 command.c:201 script_debug(): command - STM32H753ZITx.dap apreg 0 0xF8
Debug: 438 3895 command.c:201 script_debug(): command - expr $base_addr & 0xFFFFF000 | 0xFD0
User : 439 3897 gdb_server.c:755 gdb_output(): O.K.:0xE00FEFD0
Debug: 440 3897 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $O4f2e4b2e3a307845303046454644300a#db'
User : 441 3898 gdb_server.c:755 gdb_output(): 
Debug: 442 3898 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $O0a#e0'
Debug: 443 3914 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $OK#9a'
Debug: 444 3932 gdb_server.c:384 gdb_log_incoming_packet(): received packet: me00fefd0,20
Debug: 445 3932 gdb_server.c:1495 gdb_read_memory_packet(): addr: 0x00000000e00fefd0, len: 0x00000020
Debug: 446 3933 target.c:2467 target_read_buffer(): reading buffer of 32 byte at 0xe00fefd0
Debug: 447 3933 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $0000000000000000000000000000000050000000040000000a00000000000000#3a'
Debug: 448 3948 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qXfer:threads:read::0,1000
Debug: 449 3948 gdb_server.c:394 gdb_log_outgoing_packet(): sending packet: $<binary-data-44-bytes>#02
Debug: 450 3964 gdb_server.c:384 gdb_log_incoming_packet(): received packet: m0,4
Debug: 451 3964 gdb_server.c:1495 gdb_read_memory_packet(): addr: 0x0000000000000000, len: 0x00000004
Debug: 452 3964 target.c:2467 target_read_buffer(): reading buffer of 4 byte at 0x00000000
Debug: 453 3965 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $0696924c#d7'
Debug: 454 3967 gdb_server.c:384 gdb_log_incoming_packet(): received packet: m0,4
Debug: 455 3967 gdb_server.c:1495 gdb_read_memory_packet(): addr: 0x0000000000000000, len: 0x00000004
Debug: 456 3968 target.c:2467 target_read_buffer(): reading buffer of 4 byte at 0x00000000
Debug: 457 3969 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $0696924c#d7'
Debug: 458 4014 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qXfer:threads:read::0,1000
Debug: 459 4015 gdb_server.c:394 gdb_log_outgoing_packet(): sending packet: $<binary-data-44-bytes>#02
Debug: 460 4025 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qXfer:threads:read::0,1000
Debug: 461 4026 gdb_server.c:394 gdb_log_outgoing_packet(): sending packet: $<binary-data-44-bytes>#02
Info : 462 6004 server.c:101 add_connection(): accepting 'gdb' connection on tcp/3333
Debug: 463 6005 breakpoints.c:381 breakpoint_clear_target_internal(): Delete all breakpoints for target: STM32H753ZITx.cm7
Debug: 464 6006 breakpoints.c:569 watchpoint_clear_target(): Delete all watchpoints for target: STM32H753ZITx.cm7
Debug: 465 6018 target.c:1838 target_call_event_callbacks(): target event 22 (gdb-attach) for core STM32H753ZITx.cm7
Debug: 466 6019 target.c:4817 target_handle_event(): target(1): STM32H753ZITx.cm7 (cortex_m) event: 22 (gdb-attach) action: 
		global _CONNECT_UNDER_RESET

		# Needed to be able to use the connect_assert_srst in reset_config
		if { $_CONNECT_UNDER_RESET == 1 } {
			reset init
		} else {
			if { [set $_CHIPNAME.DUAL_CORE] } {
				soft_reset_halt
			}
		}
	
Debug: 467 6021 command.c:201 script_debug(): command - reset init
Debug: 468 6022 target.c:1856 target_call_reset_callbacks(): target reset 3 (init)
Debug: 469 6023 target.c:1856 target_call_reset_callbacks(): target reset 3 (init)
Debug: 470 6023 command.c:201 script_debug(): command - expr [catch {ocd_process_reset_inner $MODE} result] == 0
Debug: 471 6024 command.c:201 script_debug(): command - target names
Debug: 472 6024 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event reset-start
Debug: 473 6024 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event reset-start
Debug: 474 6025 command.c:201 script_debug(): command - transport select
Debug: 475 6025 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 476 6026 command.c:201 script_debug(): command - transport select
Debug: 477 6026 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 478 6027 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event examine-start
Debug: 479 6028 command.c:201 script_debug(): command - STM32H753ZITx.ap2 arp_examine allow-defer
Debug: 480 6028 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event examine-end
Debug: 481 6029 command.c:201 script_debug(): command - transport select
Debug: 482 6029 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 483 6029 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event examine-start
Debug: 484 6030 command.c:201 script_debug(): command - STM32H753ZITx.cm7 arp_examine allow-defer
Debug: 485 6033 arm_adi_v5.c:817 mem_ap_init(): MEM_AP Packed Transfers: disabled
Debug: 486 6033 arm_adi_v5.c:828 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0
Debug: 487 6033 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event examine-end
Debug: 488 6034 target.c:4817 target_handle_event(): target(1): STM32H753ZITx.cm7 (cortex_m) event: 21 (examine-end) action: 
		global _CHIPNAME
		global $_CHIPNAME.USE_CTI

		if { ![using_hla] } {
			# Disable corresponding CTI by default
			stm32h7x_cti_stop_one cm7_cti
		
			stm32h7x_dbgmcu_init
		}

		if { [set $_CHIPNAME.USE_CTI] } {
			stm32h7x_cti_start_cm7_cti
		}
	
Debug: 489 6036 command.c:201 script_debug(): command - transport select
Debug: 490 6036 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 491 6036 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti write INACK 0x01
Debug: 492 6038 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti write INACK 0x00
Debug: 493 6040 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti write INEN0 0
Debug: 494 6041 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti write OUTEN0 0
Debug: 495 6042 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti enable off
Debug: 496 6043 command.c:201 script_debug(): command - transport select
Debug: 497 6044 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 498 6044 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 499 6045 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759017988 1
Debug: 500 6045 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1004; size 4; count 1
Debug: 501 6046 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 502 6047 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759017988 7340095
Debug: 503 6048 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1004; size 4; count 1
Debug: 504 6049 command.c:201 script_debug(): command - transport select
Debug: 505 6049 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 506 6050 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 507 6050 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759017988 1
Debug: 508 6051 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1004; size 4; count 1
Debug: 509 6052 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 510 6053 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759017988 7340095
Debug: 511 6053 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1004; size 4; count 1
Debug: 512 6054 command.c:201 script_debug(): command - transport select
Debug: 513 6055 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 514 6055 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 515 6056 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759017988 1
Debug: 516 6056 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1004; size 4; count 1
Debug: 517 6058 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 518 6058 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759017988 7340095
Debug: 519 6059 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1004; size 4; count 1
Debug: 520 6062 command.c:201 script_debug(): command - transport select
Debug: 521 6062 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 522 6062 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 523 6063 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759018036 1
Debug: 524 6063 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1034; size 4; count 1
Debug: 525 6065 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 526 6066 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759018036 64
Debug: 527 6067 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1034; size 4; count 1
Debug: 528 6068 command.c:201 script_debug(): command - transport select
Debug: 529 6069 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 530 6070 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 531 6070 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759018044 1
Debug: 532 6070 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e103c; size 4; count 1
Debug: 533 6072 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 534 6072 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759018044 2048
Debug: 535 6073 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e103c; size 4; count 1
Debug: 536 6074 command.c:201 script_debug(): command - transport select
Debug: 537 6075 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 538 6076 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 539 6076 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759018068 1
Debug: 540 6077 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1054; size 4; count 1
Debug: 541 6079 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 542 6080 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759018068 786432
Debug: 543 6080 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1054; size 4; count 1
Debug: 544 6082 command.c:201 script_debug(): command - transport select
Debug: 545 6083 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 546 6083 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 547 6084 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759017988 1
Debug: 548 6084 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1004; size 4; count 1
Debug: 549 6086 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 550 6087 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759017988 7340095
Debug: 551 6087 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1004; size 4; count 1
Debug: 552 6095 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event reset-assert-pre
Debug: 553 6096 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event reset-assert-pre
Debug: 554 6097 command.c:201 script_debug(): command - transport select
Debug: 555 6097 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 556 6098 command.c:201 script_debug(): command - STM32H753ZITx.ap2 arp_reset assert 1
Debug: 557 6099 target.c:2194 target_free_all_working_areas_restore(): freeing all working areas
Debug: 558 6099 mem_ap.c:133 mem_ap_assert_reset(): mem_ap_assert_reset
Debug: 559 6100 command.c:201 script_debug(): command - transport select
Debug: 560 6100 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 561 6100 command.c:201 script_debug(): command - STM32H753ZITx.cm7 arp_reset assert 1
Debug: 562 6100 target.c:2194 target_free_all_working_areas_restore(): freeing all working areas
Debug: 563 6101 cortex_m.c:1162 cortex_m_assert_reset(): target->state: running
Debug: 564 6101 stlink_usb.c:5167 stlink_dap_reset(): stlink_dap_reset(1)
Debug: 565 6102 core.c:639 adapter_system_reset(): SRST line asserted
Debug: 566 6189 cortex_m.c:742 cortex_m_halt(): target->state: reset
Debug: 567 6190 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event reset-assert-post
Debug: 568 6190 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event reset-assert-post
Debug: 569 6191 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event reset-deassert-pre
Debug: 570 6191 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event reset-deassert-pre
Debug: 571 6192 command.c:201 script_debug(): command - transport select
Debug: 572 6192 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 573 6193 command.c:201 script_debug(): command - STM32H753ZITx.ap2 arp_reset deassert 1
Debug: 574 6193 target.c:2194 target_free_all_working_areas_restore(): freeing all working areas
Debug: 575 6194 target.c:1838 target_call_event_callbacks(): target event 0 (gdb-halt) for core STM32H753ZITx.ap2
Debug: 576 6194 target.c:1838 target_call_event_callbacks(): target event 1 (halted) for core STM32H753ZITx.ap2
Debug: 577 6195 mem_ap.c:86 mem_ap_arch_state(): mem_ap_arch_state
Debug: 578 6195 mem_ap.c:163 mem_ap_deassert_reset(): mem_ap_deassert_reset
Debug: 579 6195 command.c:201 script_debug(): command - transport select
Debug: 580 6196 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 581 6196 command.c:201 script_debug(): command - STM32H753ZITx.cm7 arp_reset deassert 1
Debug: 582 6198 target.c:2194 target_free_all_working_areas_restore(): freeing all working areas
Debug: 583 6198 cortex_m.c:1313 cortex_m_deassert_reset(): target->state: reset
Debug: 584 6198 stlink_usb.c:5167 stlink_dap_reset(): stlink_dap_reset(0)
Debug: 585 6199 core.c:643 adapter_system_reset(): SRST line released
Debug: 586 6362 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event reset-deassert-post
Debug: 587 6362 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event reset-deassert-post
Debug: 588 6363 command.c:201 script_debug(): command - transport select
Debug: 589 6363 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 590 6364 command.c:201 script_debug(): command - STM32H753ZITx.ap2 was_examined
Debug: 591 6364 command.c:201 script_debug(): command - STM32H753ZITx.ap2 arp_waitstate halted 1000
Debug: 592 6365 command.c:201 script_debug(): command - STM32H753ZITx.ap2 curstate
Debug: 593 6365 command.c:201 script_debug(): command - transport select
Debug: 594 6365 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 595 6366 command.c:201 script_debug(): command - STM32H753ZITx.cm7 was_examined
Debug: 596 6366 command.c:201 script_debug(): command - STM32H753ZITx.cm7 arp_waitstate halted 1000
Debug: 597 6368 cortex_m.c:681 cortex_m_poll(): Exit from reset with dcb_dhcsr 0x1010001
Debug: 598 6369 cortex_m.c:361 cortex_m_endreset_event(): DCB_DEMCR = 0x01000501
Debug: 599 6370 stlink_usb.c:4382 stlink_usb_misc_rw_segment(): Queue: 2 commands in 4 items
Debug: 600 6371 target.c:2705 target_write_u32(): address: 0xe0002000, value: 0x00000003
Debug: 601 6372 stlink_usb.c:4382 stlink_usb_misc_rw_segment(): Queue: 2 commands in 5 items
Debug: 602 6373 target.c:2617 target_read_u32(): address: 0xe0002000, value: 0x10000081
Debug: 603 6373 target.c:2705 target_write_u32(): address: 0xe0002008, value: 0x00000000
Debug: 604 6374 target.c:2705 target_write_u32(): address: 0xe000200c, value: 0x00000000
Debug: 605 6376 target.c:2705 target_write_u32(): address: 0xe0002010, value: 0x00000000
Debug: 606 6377 target.c:2705 target_write_u32(): address: 0xe0002014, value: 0x00000000
Debug: 607 6379 target.c:2705 target_write_u32(): address: 0xe0002018, value: 0x00000000
Debug: 608 6380 target.c:2705 target_write_u32(): address: 0xe000201c, value: 0x00000000
Debug: 609 6381 target.c:2705 target_write_u32(): address: 0xe0002020, value: 0x00000000
Debug: 610 6382 target.c:2705 target_write_u32(): address: 0xe0002024, value: 0x00000000
Debug: 611 6384 target.c:2705 target_write_u32(): address: 0xe0001020, value: 0x00000000
Debug: 612 6385 target.c:2705 target_write_u32(): address: 0xe0001024, value: 0x00000000
Debug: 613 6386 target.c:2705 target_write_u32(): address: 0xe0001028, value: 0x00000000
Debug: 614 6387 target.c:2705 target_write_u32(): address: 0xe0001030, value: 0x00000000
Debug: 615 6388 target.c:2705 target_write_u32(): address: 0xe0001034, value: 0x00000000
Debug: 616 6389 target.c:2705 target_write_u32(): address: 0xe0001038, value: 0x00000000
Debug: 617 6391 target.c:2705 target_write_u32(): address: 0xe0001040, value: 0x00000000
Debug: 618 6392 target.c:2705 target_write_u32(): address: 0xe0001044, value: 0x00000000
Debug: 619 6392 target.c:2705 target_write_u32(): address: 0xe0001048, value: 0x00000000
Debug: 620 6394 target.c:2705 target_write_u32(): address: 0xe0001050, value: 0x00000000
Debug: 621 6395 target.c:2705 target_write_u32(): address: 0xe0001054, value: 0x00000000
Debug: 622 6397 target.c:2705 target_write_u32(): address: 0xe0001058, value: 0x00000000
Debug: 623 6399 target.c:3274 target_wait_state(): waiting for target halted...
Error: 625 7400 target.c:3282 target_wait_state(): timed out while waiting for target halted
Debug: 626 7400 command.c:201 script_debug(): command - STM32H753ZITx.cm7 curstate
Debug: 628 7401 command.c:591 run_command(): Command 'reset' failed with error code -4
User : 629 7401 target.c:4842 target_handle_event(): Error executing event gdb-attach on target STM32H753ZITx.cm7:
TARGET: STM32H753ZITx.cm7 - Not halted
Info : 630 7402 gdb_server.c:1047 gdb_new_connection(): New GDB Connection: 2, Target STM32H753ZITx.cm7, state: running
Warn : 631 7402 gdb_server.c:1062 gdb_new_connection(): GDB connection 2 on target STM32H753ZITx.cm7 not halted
Debug: 632 7403 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qSupported:multiprocess+;swbreak+;hwbreak+;qRelocInsn+;fork-events+;vfork-events+;exec-events+;vContSupported+;QThreadEvents+;no-resumed+
Debug: 633 7404 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $PacketSize=4000;qXfer:memory-map:read+;qXfer:features:read+;qXfer:threads:read+;QStartNoAckMode+;vContSupported+#02'
Debug: 634 7407 gdb_server.c:384 gdb_log_incoming_packet(): received packet: vMustReplyEmpty
Debug: 635 7407 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $#00'
Debug: 636 7409 gdb_server.c:384 gdb_log_incoming_packet(): received packet: QStartNoAckMode
Debug: 637 7409 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $OK#9a'
Debug: 638 7411 gdb_server.c:676 gdb_get_packet_inner(): Received first acknowledgment after entering noack mode. Ignoring it.
Debug: 639 7411 gdb_server.c:384 gdb_log_incoming_packet(): received packet: !
Debug: 640 7412 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $OK#9a'
Debug: 641 7413 gdb_server.c:384 gdb_log_incoming_packet(): received packet: Hg0
Debug: 642 7413 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $OK#9a'
Debug: 643 7414 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qXfer:features:read:target.xml:0,1000
Debug: 644 7417 gdb_server.c:394 gdb_log_outgoing_packet(): sending packet: $<binary-data-3942-bytes>#d1
Debug: 645 7419 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qTStatus
Debug: 646 7419 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $#00'
Debug: 647 7420 gdb_server.c:384 gdb_log_incoming_packet(): received packet: ?
Debug: 648 7421 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $S02#b5'
Debug: 649 7422 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qXfer:threads:read::0,1000
Debug: 650 7422 gdb_server.c:394 gdb_log_outgoing_packet(): sending packet: $<binary-data-44-bytes>#02
Debug: 651 7424 gdb_server.c:384 gdb_log_incoming_packet(): received packet: Hc-1
Debug: 652 7424 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $OK#9a'
Debug: 653 7425 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qC
Debug: 654 7425 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $QC0#c4'
Debug: 655 7427 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qAttached
Debug: 656 7427 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $1#31'
Debug: 657 7428 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qOffsets
Debug: 658 7429 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $Text=0;Data=0;Bss=0#04'
Debug: 659 7430 gdb_server.c:384 gdb_log_incoming_packet(): received packet: g
Debug: 660 7431 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000#80'
Debug: 661 7433 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qXfer:memory-map:read::0,1000
Debug: 662 7433 gdb_server.c:394 gdb_log_outgoing_packet(): sending packet: $<binary-data-378-bytes>#ce
Debug: 663 7434 gdb_server.c:384 gdb_log_incoming_packet(): received packet: m8018ecc,2
Debug: 664 7435 gdb_server.c:1495 gdb_read_memory_packet(): addr: 0x0000000008018ecc, len: 0x00000002
Debug: 665 7435 target.c:2467 target_read_buffer(): reading buffer of 2 byte at 0x08018ecc
Debug: 666 7437 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $08b5#ff'
Debug: 667 7438 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qXfer:threads:read::0,1000
Debug: 668 7439 gdb_server.c:394 gdb_log_outgoing_packet(): sending packet: $<binary-data-44-bytes>#02
Debug: 669 7440 gdb_server.c:384 gdb_log_incoming_packet(): received packet: m0,4
Debug: 670 7440 gdb_server.c:1495 gdb_read_memory_packet(): addr: 0x0000000000000000, len: 0x00000004
Debug: 671 7441 target.c:2467 target_read_buffer(): reading buffer of 4 byte at 0x00000000
Debug: 672 7442 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $0696924c#d7'
Debug: 673 7444 gdb_server.c:384 gdb_log_incoming_packet(): received packet: qSymbol::
Debug: 674 7444 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $OK#9a'
Debug: 675 7472 gdb_server.c:384 gdb_log_incoming_packet(): received packet: vFlashErase:08000000,00060000
Debug: 676 7473 target.c:1838 target_call_event_callbacks(): target event 24 (gdb-flash-erase-start) for core STM32H753ZITx.cm7
Debug: 677 7473 target.c:4817 target_handle_event(): target(1): STM32H753ZITx.cm7 (cortex_m) event: 24 (gdb-flash-erase-start) action: reset init
Debug: 678 7474 command.c:201 script_debug(): command - reset init
Debug: 679 7476 target.c:1856 target_call_reset_callbacks(): target reset 3 (init)
Debug: 680 7477 target.c:1856 target_call_reset_callbacks(): target reset 3 (init)
Debug: 681 7477 command.c:201 script_debug(): command - expr [catch {ocd_process_reset_inner $MODE} result] == 0
Debug: 682 7478 command.c:201 script_debug(): command - target names
Debug: 683 7479 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event reset-start
Debug: 684 7479 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event reset-start
Debug: 685 7480 command.c:201 script_debug(): command - transport select
Debug: 686 7480 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 687 7481 command.c:201 script_debug(): command - transport select
Debug: 688 7481 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 689 7482 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event examine-start
Debug: 690 7482 command.c:201 script_debug(): command - STM32H753ZITx.ap2 arp_examine allow-defer
Debug: 691 7483 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event examine-end
Debug: 692 7483 command.c:201 script_debug(): command - transport select
Debug: 693 7484 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 694 7484 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event examine-start
Debug: 695 7485 command.c:201 script_debug(): command - STM32H753ZITx.cm7 arp_examine allow-defer
Debug: 696 7487 arm_adi_v5.c:817 mem_ap_init(): MEM_AP Packed Transfers: disabled
Debug: 697 7488 arm_adi_v5.c:828 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0
Debug: 698 7488 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event examine-end
Debug: 699 7489 target.c:4817 target_handle_event(): target(1): STM32H753ZITx.cm7 (cortex_m) event: 21 (examine-end) action: 
		global _CHIPNAME
		global $_CHIPNAME.USE_CTI

		if { ![using_hla] } {
			# Disable corresponding CTI by default
			stm32h7x_cti_stop_one cm7_cti
		
			stm32h7x_dbgmcu_init
		}

		if { [set $_CHIPNAME.USE_CTI] } {
			stm32h7x_cti_start_cm7_cti
		}
	
Debug: 700 7490 command.c:201 script_debug(): command - transport select
Debug: 701 7490 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 702 7491 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti write INACK 0x01
Debug: 703 7493 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti write INACK 0x00
Debug: 704 7494 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti write INEN0 0
Debug: 705 7496 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti write OUTEN0 0
Debug: 706 7498 command.c:201 script_debug(): command - STM32H753ZITx.cm7_cti enable off
Debug: 707 7499 command.c:201 script_debug(): command - transport select
Debug: 708 7499 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 709 7500 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 710 7500 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759017988 1
Debug: 711 7501 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1004; size 4; count 1
Debug: 712 7502 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 713 7503 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759017988 7340095
Debug: 714 7503 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1004; size 4; count 1
Debug: 715 7505 command.c:201 script_debug(): command - transport select
Debug: 716 7505 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 717 7505 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 718 7506 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759017988 1
Debug: 719 7506 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1004; size 4; count 1
Debug: 720 7508 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 721 7508 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759017988 7340095
Debug: 722 7509 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1004; size 4; count 1
Debug: 723 7512 command.c:201 script_debug(): command - transport select
Debug: 724 7512 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 725 7513 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 726 7514 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759017988 1
Debug: 727 7514 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1004; size 4; count 1
Debug: 728 7518 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 729 7519 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759017988 7340095
Debug: 730 7520 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1004; size 4; count 1
Debug: 731 7522 command.c:201 script_debug(): command - transport select
Debug: 732 7522 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 733 7523 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 734 7524 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759018036 1
Debug: 735 7524 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1034; size 4; count 1
Debug: 736 7527 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 737 7527 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759018036 64
Debug: 738 7528 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1034; size 4; count 1
Debug: 739 7530 command.c:201 script_debug(): command - transport select
Debug: 740 7530 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 741 7531 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 742 7532 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759018044 1
Debug: 743 7532 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e103c; size 4; count 1
Debug: 744 7534 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 745 7534 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759018044 2048
Debug: 746 7535 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e103c; size 4; count 1
Debug: 747 7537 command.c:201 script_debug(): command - transport select
Debug: 748 7537 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 749 7538 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 750 7538 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759018068 1
Debug: 751 7539 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1054; size 4; count 1
Debug: 752 7540 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 753 7541 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759018068 786432
Debug: 754 7542 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1054; size 4; count 1
Debug: 755 7543 command.c:201 script_debug(): command - transport select
Debug: 756 7544 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 757 7544 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 758 7545 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759017988 1
Debug: 759 7545 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e1004; size 4; count 1
Debug: 760 7547 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 761 7547 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759017988 7340095
Debug: 762 7548 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e1004; size 4; count 1
Debug: 763 7549 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event reset-assert-pre
Debug: 764 7550 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event reset-assert-pre
Debug: 765 7550 command.c:201 script_debug(): command - transport select
Debug: 766 7551 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 767 7552 command.c:201 script_debug(): command - STM32H753ZITx.ap2 arp_reset assert 1
Debug: 768 7552 target.c:2194 target_free_all_working_areas_restore(): freeing all working areas
Debug: 769 7552 mem_ap.c:133 mem_ap_assert_reset(): mem_ap_assert_reset
Debug: 770 7552 command.c:201 script_debug(): command - transport select
Debug: 771 7553 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 772 7553 command.c:201 script_debug(): command - STM32H753ZITx.cm7 arp_reset assert 1
Debug: 773 7554 target.c:2194 target_free_all_working_areas_restore(): freeing all working areas
Debug: 774 7554 cortex_m.c:1162 cortex_m_assert_reset(): target->state: running
Debug: 775 7555 stlink_usb.c:5167 stlink_dap_reset(): stlink_dap_reset(1)
Debug: 776 7555 core.c:639 adapter_system_reset(): SRST line asserted
Debug: 777 7641 cortex_m.c:742 cortex_m_halt(): target->state: reset
Debug: 778 7641 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event reset-assert-post
Debug: 779 7642 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event reset-assert-post
Debug: 780 7642 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event reset-deassert-pre
Debug: 781 7643 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event reset-deassert-pre
Debug: 782 7644 command.c:201 script_debug(): command - transport select
Debug: 783 7644 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 784 7645 command.c:201 script_debug(): command - STM32H753ZITx.ap2 arp_reset deassert 1
Debug: 785 7646 target.c:2194 target_free_all_working_areas_restore(): freeing all working areas
Debug: 786 7646 target.c:1838 target_call_event_callbacks(): target event 0 (gdb-halt) for core STM32H753ZITx.ap2
Debug: 787 7646 target.c:1838 target_call_event_callbacks(): target event 1 (halted) for core STM32H753ZITx.ap2
Debug: 788 7647 mem_ap.c:86 mem_ap_arch_state(): mem_ap_arch_state
Debug: 789 7647 mem_ap.c:163 mem_ap_deassert_reset(): mem_ap_deassert_reset
Debug: 790 7648 command.c:201 script_debug(): command - transport select
Debug: 791 7648 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 792 7649 command.c:201 script_debug(): command - STM32H753ZITx.cm7 arp_reset deassert 1
Debug: 793 7649 target.c:2194 target_free_all_working_areas_restore(): freeing all working areas
Debug: 794 7649 cortex_m.c:1313 cortex_m_deassert_reset(): target->state: reset
Debug: 795 7650 stlink_usb.c:5167 stlink_dap_reset(): stlink_dap_reset(0)
Debug: 796 7657 core.c:643 adapter_system_reset(): SRST line released
Debug: 797 7812 command.c:201 script_debug(): command - STM32H753ZITx.ap2 invoke-event reset-deassert-post
Debug: 798 7812 command.c:201 script_debug(): command - STM32H753ZITx.cm7 invoke-event reset-deassert-post
Debug: 799 7813 command.c:201 script_debug(): command - transport select
Debug: 800 7813 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 801 7814 command.c:201 script_debug(): command - STM32H753ZITx.ap2 was_examined
Debug: 802 7815 command.c:201 script_debug(): command - STM32H753ZITx.ap2 arp_waitstate halted 1000
Debug: 803 7815 command.c:201 script_debug(): command - STM32H753ZITx.ap2 curstate
Debug: 804 7816 command.c:201 script_debug(): command - transport select
Debug: 805 7816 command.c:201 script_debug(): command - expr  [ string first "jtag" $_TRANSPORT ] != -1 
Debug: 806 7817 command.c:201 script_debug(): command - STM32H753ZITx.cm7 was_examined
Debug: 807 7818 command.c:201 script_debug(): command - STM32H753ZITx.cm7 arp_waitstate halted 1000
Debug: 808 7822 cortex_m.c:681 cortex_m_poll(): Exit from reset with dcb_dhcsr 0x1010001
Debug: 809 7823 cortex_m.c:361 cortex_m_endreset_event(): DCB_DEMCR = 0x01000501
Debug: 810 7823 stlink_usb.c:4382 stlink_usb_misc_rw_segment(): Queue: 2 commands in 4 items
Debug: 811 7825 target.c:2705 target_write_u32(): address: 0xe0002000, value: 0x00000003
Debug: 812 7825 stlink_usb.c:4382 stlink_usb_misc_rw_segment(): Queue: 2 commands in 5 items
Debug: 813 7831 target.c:2617 target_read_u32(): address: 0xe0002000, value: 0x10000081
Debug: 814 7832 target.c:2705 target_write_u32(): address: 0xe0002008, value: 0x00000000
Debug: 815 7833 target.c:2705 target_write_u32(): address: 0xe000200c, value: 0x00000000
Debug: 816 7836 target.c:2705 target_write_u32(): address: 0xe0002010, value: 0x00000000
Debug: 817 7837 target.c:2705 target_write_u32(): address: 0xe0002014, value: 0x00000000
Debug: 818 7839 target.c:2705 target_write_u32(): address: 0xe0002018, value: 0x00000000
Debug: 819 7840 target.c:2705 target_write_u32(): address: 0xe000201c, value: 0x00000000
Debug: 820 7841 target.c:2705 target_write_u32(): address: 0xe0002020, value: 0x00000000
Debug: 821 7842 target.c:2705 target_write_u32(): address: 0xe0002024, value: 0x00000000
Debug: 822 7844 target.c:2705 target_write_u32(): address: 0xe0001020, value: 0x00000000
Debug: 823 7847 target.c:2705 target_write_u32(): address: 0xe0001024, value: 0x00000000
Debug: 824 7849 target.c:2705 target_write_u32(): address: 0xe0001028, value: 0x00000000
Debug: 825 7850 target.c:2705 target_write_u32(): address: 0xe0001030, value: 0x00000000
Debug: 826 7851 target.c:2705 target_write_u32(): address: 0xe0001034, value: 0x00000000
Debug: 827 7853 target.c:2705 target_write_u32(): address: 0xe0001038, value: 0x00000000
Debug: 828 7854 target.c:2705 target_write_u32(): address: 0xe0001040, value: 0x00000000
Debug: 829 7855 target.c:2705 target_write_u32(): address: 0xe0001044, value: 0x00000000
Debug: 830 7856 target.c:2705 target_write_u32(): address: 0xe0001048, value: 0x00000000
Debug: 831 7857 target.c:2705 target_write_u32(): address: 0xe0001050, value: 0x00000000
Debug: 832 7858 target.c:2705 target_write_u32(): address: 0xe0001054, value: 0x00000000
Debug: 833 7860 target.c:2705 target_write_u32(): address: 0xe0001058, value: 0x00000000
Debug: 834 7863 target.c:3274 target_wait_state(): waiting for target halted...
Error: 836 8864 target.c:3282 target_wait_state(): timed out while waiting for target halted
Debug: 837 8864 command.c:201 script_debug(): command - STM32H753ZITx.cm7 curstate
Debug: 838 8865 command.c:591 run_command(): Command 'reset' failed with error code -4
User : 839 8865 target.c:4842 target_handle_event(): Error executing event gdb-flash-erase-start on target STM32H753ZITx.cm7:
TARGET: STM32H753ZITx.cm7 - Not halted
Error: 840 8866 core.c:47 flash_driver_erase(): failed erasing sectors 0 to 2
Debug: 841 8866 target.c:1838 target_call_event_callbacks(): target event 25 (gdb-flash-erase-end) for core STM32H753ZITx.cm7
Debug: 842 8867 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $E05#aa'
Error: 843 8868 gdb_server.c:3122 gdb_v_packet(): flash_erase returned -304
Debug: 844 8887 gdb_server.c:384 gdb_log_incoming_packet(): received packet: D
Debug: 845 8887 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $OK#9a'
Debug: 846 8889 gdb_server.c:384 gdb_log_incoming_packet(): received packet: ?
Debug: 847 8889 gdb_server.c:396 gdb_log_outgoing_packet(): sending packet: $S02#b5'
Debug: 848 8892 gdb_server.c:1090 gdb_connection_closed(): GDB Close, Target: STM32H753ZITx.cm7, state: running, gdb_actual_connections=1
Debug: 849 8893 target.c:1838 target_call_event_callbacks(): target event 8 (gdb-end) for core STM32H753ZITx.cm7
Debug: 850 8894 target.c:1838 target_call_event_callbacks(): target event 23 (gdb-detach) for core STM32H753ZITx.cm7
Debug: 851 8895 target.c:4817 target_handle_event(): target(1): STM32H753ZITx.cm7 (cortex_m) event: 23 (gdb-detach) action: 
		global _CHIPNAME
		global $_CHIPNAME.USE_CTI

		if { [set $_CHIPNAME.USE_CTI] } {
			stm32h7x_cti_stop_one cm7_cti
		}

		# Disable CM7 slave port in SWO trace Funnel
		# Hack, use stm32h7x_dbgmcu_mmw with big offset to control SWTF
		# SWTF_CTRL |= ~ENS0
		stm32h7x_dbgmcu_mmw 0x3000 0 0x00000001

		# to close connection if debug mode entered
		if { [info exists AP_NUM] && ($AP_NUM == 0) } {
			shutdown
		}
	
Debug: 852 8898 command.c:201 script_debug(): command - transport select
Debug: 853 8899 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 854 8902 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 855 8907 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759030272 1
Debug: 856 8918 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e4000; size 4; count 1
Debug: 857 8920 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 858 8921 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759030272 768
Debug: 859 8923 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e4000; size 4; count 1
Debug: 860 8928 command.c:201 script_debug(): command - shutdown
User : 861 8930 server.c:759 handle_shutdown_command(): shutdown command invoked
Info : 862 8930 server.c:581 server_loop(): dropped 'gdb' connection
Debug: 863 8931 gdb_server.c:1090 gdb_connection_closed(): GDB Close, Target: STM32H753ZITx.cm7, state: running, gdb_actual_connections=0
Debug: 864 8932 target.c:1838 target_call_event_callbacks(): target event 8 (gdb-end) for core STM32H753ZITx.cm7
Debug: 865 8933 target.c:1838 target_call_event_callbacks(): target event 23 (gdb-detach) for core STM32H753ZITx.cm7
Debug: 866 8933 target.c:4817 target_handle_event(): target(1): STM32H753ZITx.cm7 (cortex_m) event: 23 (gdb-detach) action: 
		global _CHIPNAME
		global $_CHIPNAME.USE_CTI

		if { [set $_CHIPNAME.USE_CTI] } {
			stm32h7x_cti_stop_one cm7_cti
		}

		# Disable CM7 slave port in SWO trace Funnel
		# Hack, use stm32h7x_dbgmcu_mmw with big offset to control SWTF
		# SWTF_CTRL |= ~ENS0
		stm32h7x_dbgmcu_mmw 0x3000 0 0x00000001

		# to close connection if debug mode entered
		if { [info exists AP_NUM] && ($AP_NUM == 0) } {
			shutdown
		}
	
Debug: 867 8936 command.c:201 script_debug(): command - transport select
Debug: 868 8938 command.c:201 script_debug(): command - expr  [ string first "hla" $_TRANSPORT ] != -1 
Debug: 869 8939 command.c:201 script_debug(): command - expr 0xE00E1000 + $reg_offset
Debug: 870 8941 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mem2array value 32 3759030272 1
Debug: 871 8942 mem_ap.c:239 mem_ap_read_memory(): Reading memory at physical address 0xe00e4000; size 4; count 1
Debug: 872 8945 command.c:201 script_debug(): command - expr ($old & ~$clearbits) | $setbits
Debug: 873 8946 command.c:201 script_debug(): command - STM32H753ZITx.ap2 mww 3759030272 768
Debug: 874 8948 mem_ap.c:254 mem_ap_write_memory(): Writing memory at physical address 0xe00e4000; size 4; count 1
Debug: 875 8949 command.c:201 script_debug(): command - shutdown
User : 876 8950 server.c:759 handle_shutdown_command(): shutdown command invoked
Debug: 877 8951 mem_ap.c:77 mem_ap_deinit_target(): mem_ap_deinit_target
Debug: 878 8952 target.c:2194 target_free_all_working_areas_restore(): freeing all working areas
Debug: 879 8952 target.c:2194 target_free_all_working_areas_restore(): freeing all working areas
Debug: 880 8954 stlink_usb.c:5156 stlink_dap_quit(): stlink_dap_quit()
Debug: 881 8955 stlink_usb.c:1653 stlink_usb_exit_mode(): MODE: 0x02

Debug Level 0

0.11.0+dev-00438-ga75fc63 (2021-11-03-15:27)

Open On-Chip Debugger 0.11.0+dev-00438-ga75fc63 (2021-11-03-15:27)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
stm32h7x_cti_prepare_restart_one
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : STLINK V3J9M3 (API v3) VID:PID 0483:374E
Info : Target voltage: 3.281275
Info : clock speed 8000 kHz
Info : stlink_dap_op_connect(connect)
Info : SWD DPIDR 0x6ba02477
Info : STM32H753ZITx.cm7: Cortex-M7 r1p1 processor detected
Info : STM32H753ZITx.cm7: target has 8 breakpoints, 4 watchpoints
Info : gdb port disabled
Info : starting gdb server for STM32H753ZITx.cm7 on 3333
Info : Listening on port 3333 for gdb connections
Info : accepting 'gdb' connection on tcp/3333
Error: timed out while waiting for target halted
Error executing event gdb-attach on target STM32H753ZITx.cm7:
TARGET: STM32H753ZITx.cm7 - Not halted
Info : Device: STM32H74x/75x
Info : flash size probed value 2048k
Info : STM32H7 flash has dual banks
Info : Bank (0) size is 1024 kb, base address is 0x08000000
Info : Device: STM32H74x/75x
Info : flash size probed value 2048k
Info : STM32H7 flash has dual banks
Info : Bank (1) size is 1024 kb, base address is 0x08100000
Info : New GDB Connection: 1, Target STM32H753ZITx.cm7, state: running
Warn : GDB connection 1 on target STM32H753ZITx.cm7 not halted
O.K.

O.K.:0xE00FEFD0

Info : accepting 'gdb' connection on tcp/3333
Error: timed out while waiting for target halted
Error executing event gdb-attach on target STM32H753ZITx.cm7:
TARGET: STM32H753ZITx.cm7 - Not halted
Info : New GDB Connection: 2, Target STM32H753ZITx.cm7, state: running
Warn : GDB connection 2 on target STM32H753ZITx.cm7 not halted
Error: timed out while waiting for target halted
Error executing event gdb-flash-erase-start on target STM32H753ZITx.cm7:
TARGET: STM32H753ZITx.cm7 - Not halted
Error: failed erasing sectors 0 to 2
Error: flash_erase returned -304
shutdown command invoked
Info : dropped 'gdb' connection
shutdown command invoked

0.11.0-rc2+dev-00044-g8340bb0 (2021-06-02-17:29)

Open On-Chip Debugger 0.11.0-rc2+dev-00044-g8340bb0 (2021-06-02-17:29)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
stm32h7x_cti_prepare_restart_one
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : STLINK V3J8M3 (API v3) VID:PID 0483:374E
Info : Target voltage: 3.273453
Info : clock speed 8000 kHz
Info : stlink_dap_op_connect(connect)
Info : SWD DPIDR 0x6ba02477
Info : STM32H753ZITx.cm7: hardware has 8 breakpoints, 4 watchpoints
Info : starting gdb server for STM32H753ZITx.cm7 on 3333
Info : Listening on port 3333 for gdb connections
Info : accepting 'gdb' connection on tcp/3333
Error: timed out while waiting for target halted
Error executing event gdb-attach on target STM32H753ZITx.cm7:
TARGET: STM32H753ZITx.cm7 - Not halted
Info : Device: STM32H74x/75x
Info : flash size probed value 2048
Info : STM32H7 flash has dual banks
Info : Bank (0) size is 1024 kb, base address is 0x08000000
Info : Device: STM32H74x/75x
Info : flash size probed value 2048
Info : STM32H7 flash has dual banks
Info : Bank (1) size is 1024 kb, base address is 0x08100000
Info : New GDB Connection: 1, Target STM32H753ZITx.cm7, state: running
Warn : GDB connection 1 on target STM32H753ZITx.cm7 not halted
Info : accepting 'gdb' connection on tcp/3333
Error: timed out while waiting for target halted
Error executing event gdb-attach on target STM32H753ZITx.cm7:
TARGET: STM32H753ZITx.cm7 - Not halted
Info : New GDB Connection: 2, Target STM32H753ZITx.cm7, state: running
Warn : GDB connection 2 on target STM32H753ZITx.cm7 not halted
Error: timed out while waiting for target halted
Error executing event gdb-flash-erase-start on target STM32H753ZITx.cm7:
TARGET: STM32H753ZITx.cm7 - Not halted
Error: failed erasing sectors 0 to 2
Error: flash_erase returned -304
shutdown command invoked
Info : dropped 'gdb' connection
shutdown command invoked

xPack OpenOCD

0.11.0+dev (2021-10-16-21:19)

xPack OpenOCD x86_64 Open On-Chip Debugger 0.11.0+dev (2021-10-16-21:19)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
stm32h7x_cti_prepare_restart_one
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : STLINK V3J8M3 (API v3) VID:PID 0483:374E
Info : Target voltage: 3.289421
Info : Unable to match requested speed 4000 kHz, using 3300 kHz
Info : Unable to match requested speed 4000 kHz, using 3300 kHz
Info : clock speed 3300 kHz
Info : stlink_dap_op_connect(connect)
Info : SWD DPIDR 0x6ba02477
Info : STM32H753ZITx.cm7: Cortex-M7 r1p1 processor detected
Info : STM32H753ZITx.cm7: target has 8 breakpoints, 4 watchpoints
Info : gdb port disabled
Info : starting gdb server for STM32H753ZITx.cm7 on 3333
Info : Listening on port 3333 for gdb connections
Info : accepting 'gdb' connection on tcp/3333
Error: timed out while waiting for target halted
Error executing event gdb-attach on target STM32H753ZITx.cm7:
TARGET: STM32H753ZITx.cm7 - Not halted
Info : Device: STM32H74x/75x
Info : flash size probed value 2048
Info : STM32H7 flash has dual banks
Info : Bank (0) size is 1024 kb, base address is 0x08000000
Info : Device: STM32H74x/75x
Info : flash size probed value 2048
Info : STM32H7 flash has dual banks
Info : Bank (1) size is 1024 kb, base address is 0x08100000
Info : New GDB Connection: 1, Target STM32H753ZITx.cm7, state: running
Warn : GDB connection 1 on target STM32H753ZITx.cm7 not halted
Info : accepting 'gdb' connection on tcp/3333
Error: timed out while waiting for target halted
Error executing event gdb-attach on target STM32H753ZITx.cm7:
TARGET: STM32H753ZITx.cm7 - Not halted
Info : New GDB Connection: 2, Target STM32H753ZITx.cm7, state: running
Warn : GDB connection 2 on target STM32H753ZITx.cm7 not halted
Error: timed out while waiting for target halted
Error executing event gdb-flash-erase-start on target STM32H753ZITx.cm7:
TARGET: STM32H753ZITx.cm7 - Not halted
Error: failed erasing sectors 0 to 2
Error: flash_erase returned -304
shutdown command invoked
Info : dropped 'gdb' connection
shutdown command invoked

Status of the fork and upstreaming changes

Hi,

since this is a fork of the original OpenOCD, I would like to know what the intended role of this fork is. Especially I would really like to have the support for newer STM32 chips upstream back into the original project, since that one is installed via the package manager.

Do you plan to upstream your work? If not, is there any problem is cherry picking any commit back to upstream?

OpenOCD with STM32L082 not handling IWDG/WWDG/STOP/SLEEP correctly

I'm using JetBrains CLion as a development environment, with OpenOCD and GDB as the flash/debug toolchain.

I have a custom board with STM32L082CZ, similar to the B-LR072-LRWAN1 board.

I have previously been using STM32CubeIDE and its integrated flash/debug facility and this has worked ok, although I was trying to switch to CLion as I found the Cube IDE performance under macOS to be poor. I also develop for other MCU with different toolchains and was looking to standardise.

I discovered that it was desirable to use the STMicroelectronics/OpenOCD openocd-cubeide-r4 release, as opposed to the openocd-org/openocd 0.11.0 release as the STML0 family was, at least at some point, not fully supported. Specifically, STM32L0 has dual memory banks and this is not configured in the stml0discovery.cfg file provided with the official openocd release. This is provided in the STM/OpenOCD release.

The specific problem I was encountering was constant disconnects/non-communication with the device. Flashing worked ok, but debugger stability was poor to non-existent. I discovered largely through trial and error that the debugger was:

Not disabling IWDG and WWDG timers when under debugger control, so if I held the programme at a breakpoint for too long the MCU would reset.
Not enabling debugger in STOP and SLEEP modes correctly, resulting in each 'step' in the debugger losing track/control of the MCU and ultimately failing to debug as required.

I altered my code to disable STOP/SLEEP states and disabled use of IWDG/WWDG and found that the debug stability vastly improved.

I followed the openocd configuration files in use, including the linkages from the dual memory config to the base config, and found that both of these processes are controlled by events within the stm32l0.cfg file. I verified that the memory addresses are correct, and the bitfield values, as per the STM docs for the MCU.

So it seems that for some reason, these settings are not being correctly applied, either not triggered at the appropriate points or the writes do not succeed.

Whilst I have worked around the problem, it would be great if this was better documented (it took me several hours of searching on forums etc to find the relevant information, plus a degree of trial and error), and whatever the reason for the failure to be resolved.

--------------------------------------------------------
st-info --probe output
--------------------------------------------------------
Found 1 stlink programmers
 version:  V2J29S7
 serial:   55FF74067880565352161467
 flash:   196608 (pagesize: 128)
 sram:    20480
 chipid:   0x0447
 descr:   L0xx Category 5

--------------------------------------------------------
config for openocd
--------------------------------------------------------

source [find interface/stlink.cfg]

transport select hla_swd

set WORKAREASIZE 0x2000

# L082 has dual bank memory
source [find target/stm32l0_dual_bank.cfg]

reset_config srst_only

# required to allow device reset when unresponsive
reset_config connect_assert_srst

--------------------------------------------------------
output for openocd (with MCU code changed to remove IWDG/WWDG/STOP/SLEEP
--------------------------------------------------------
/usr/local/bin/openocd -s /usr/local/share/openocd/scripts -f /<redacted>/SD01-L-V2/src/board/SD01-L-STM32L082/openocd/stm32l082.cfg -c "tcl_port disabled" -c "gdb_port disabled" -c "tcl_port disabled" -c "program \"/<redacted>/SD01-L-V2/dist/SD01-L-V2-0-0-1-Debug.elf\"" -c reset -c shutdown
Open On-Chip Debugger 0.11.0+dev-00454-gd3b71197b-dirty (2022-09-04-13:46) [https://github.com/STMicroelectronics/OpenOCD]
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
srst_only separate srst_nogate srst_open_drain connect_assert_srst

Info : clock speed 300 kHz
Info : STLINK V2J29S7 (API v2) VID:PID 0483:3748
Info : Target voltage: 3.245026
Info : stm32l0.cpu: Cortex-M0+ r0p1 processor detected
Info : stm32l0.cpu: target has 4 breakpoints, 2 watchpoints
Info : gdb port disabled
Info : Unable to match requested speed 300 kHz, using 240 kHz
Info : Unable to match requested speed 300 kHz, using 240 kHz
target halted due to debug-request, current mode: Thread 
xPSR: 0xf1000000 pc: 0x08010064 msp: 0x20005000
STM32L0: Enabling HSI16
Info : Unable to match requested speed 2500 kHz, using 1800 kHz
Info : Unable to match requested speed 2500 kHz, using 1800 kHz
** Programming Started **
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 96kb, base address is 0x8000000
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (1) size is 96kb, base address is 0x8018000
** Programming Finished **
Info : Unable to match requested speed 300 kHz, using 240 kHz
Info : Unable to match requested speed 300 kHz, using 240 kHz
shutdown command invoked

ST-LINK V3 fails to connect to an STM8 target

An ST-LINK V3 probe fails to work with an STM8 target. Two distinct probes were tested, and the issue appears to be OpenOCD-related. The probes work well with STM8 if the original ST utilities are used on Windows.

FYI originally reported upstream: https://sourceforge.net/p/openocd/tickets/325/

stlink_usb Assertion `handle != NULL' failed

In src/jtag/drivers/stlink_usb.c:1169 - stlink_usb_mode_leave: Assertion `handle != NULL' failed.

This happen when I try execute a mass erase command using flash erase_sector or stm32l4x mass_erase.

The null pointer is passed hardcode to the stlink_dap_arp_init function when there's a STLINK_SWD_AP_STICKY_ERROR

Target: stm32wbx
Interface: stlink

Missing commits from STM32CubeIDE 15.0 (STM32H7S support)

It appears that this repository is missing support for the STM32H7S devices that included in the build shipped with the STM32CubeIDE. The STM32CubeIDE-generated script for STM32H7S7L8HxH results in the following error with the version built from this repository:

Warn : Cannot identify target as a STM32H7xx family.
Error: auto_probe failed

Also, the binary shipped with STM32CubeIDE references a non-existing commit:

Open On-Chip Debugger 0.12.0-00029-gf77e7cb03 (2023-12-15-13:25) [https://github.com/STMicroelectronics/OpenOCD]

It would be great if you could push the missing commits into Github.

STM32F767ZG says "Cortex-M PARTNO 0x0 is unrecognized"

I am unable to connect to STM32F767ZG

Open On-Chip Debugger 0.12.0-00017-gb153daa14 (2023-02-03-14:58) [https://github.com/STMicroelectronics/OpenOCD]
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
none separate

Info : clock speed 4000 kHz
Info : STLINK V2J34S7 (API v2) VID:PID 0483:3748
Info : Target voltage: 3.254183
Error: [stm32f7x.cpu] Cortex-M PARTNO 0x0 is unrecognized
Warn : target stm32f7x.cpu examination failed
Info : starting gdb server for stm32f7x.cpu on 3333
Info : Listening on port 3333 for gdb connections
Error: [stm32f7x.cpu] Cortex-M PARTNO 0x0 is unrecognized
Error: Target not examined yet

invalid command name "hla_serial"

Hello,

as I know, the OpenOCD shall support the "hla_serial" command, it is also mentioned in AN4989 Rev 3, but STM32CubeIDE 1.10.1 still generates error: invalid command name "hla_serial".

Is it a bug or is there other way to use debugger with specific serial number?

STM32F769 based board with different QSPI pins

Hi there --

We are working on a custom board using an STM32F769BI and might choose different pins for the QSPI flash.

I'm wondering how we would need to change proc qspi_init { } for it work on different pins?

Do we need to change other things as well?

Thanks for your help!

STM32WBA missing target configuration file

In commit 54c8f87 support for the STM32WBA chip was added to the STM32L4x flash driver, unfortunately without any target configuration file.

Even with the above commit added to my local OpenOCD, I cannot flash my application into the board, as neither the existing target/stm32l4x.cfg nor target/stm32wbx.cfg work with the board. I have no prior experience with writing my own target config, so I am quite lost now. I have found the JTAG ID of the chip in the reference manual (RM0493 section 40.2.8), but cannot find the correct SWD ID. Also I am not sure what other changes need to be done to adapt an existing config file for this chip.

Can someone with more experience look into creating a working STM32WBA target config file? I noticed the same is also true for the STM32C0x chip (flash driver yes, target config no).

stm32wlx: SWOTrace not working

I have been evaluating the nucleo-wl55jc1 and have deployment and debugging working via openocd (just single core at the moment). I am currently running "xPack Open On-Chip Debugger 0.12.0+dev-01312-g18281b0c4-dirty (2023-09-04-22:31)" a very recent build by xPack.

We use SWOTrace quite extensively, especially on devices that lack UART peripherals, however I have had trouble getting it to work with target/stm32wlx.cfg. My complete configuration derived from other working f1x, f4x, l4x parts : -

`source [find interface/stlink.cfg]

transport select hla_swd

source [find target/stm32wlx.cfg]

itm port 0 on
tcl_port 6666

tpiu create stm32wlx.cpu0.tpiu -dap stm32wlx.dap -ap-num 0
stm32wlx.cpu0.tpiu configure -protocol uart -traceclk 32000000 -output swo_out -formatter off -pin-freq 1000000
stm32wlx.cpu0.tpiu enable
`

Using this configuration SWOTrace only works if I enable and use it with STMCubeIDE first, this only seems to work with the "ST-LINK (ST-LINK GDB Server)" debug probe using the SWV capabilities of the IDE. I couldn't get "ST-LINK (openocd)" to work at all. The device will then work fine with SWOTrace until I remove power to the device. I suspect there are missing register changes in the openocd configuration, this might have something to do with the dual-core nature, but I did look at scripts for other parts like stm32wb but didn't notice anything different.

Note that I found that SB8 on the dev board requires a solder bridge for SWO to be passed to the built-in STLink device.

How to use OpenOCD to debug the Cortex-M4 of STM32H7?

I was using OpenOCD & GDB to debug an STM32H745 board, which has both a Cortex-M7 and a Cortex-M4 processor. I was able to set up the GDB server for the Cortex-M7 using the following command and then connect to port 3333 to perform single-step debugging:

$ openocd -f ./tcl/interface/stlink-v2-1.cfg -f ./tcl/target/stm32h7x.cfg

However, I was unable to use this setup to debug the Cortex-M4. Can anyone offer any guidance on how to do this? Thank you in advance!

Segfault when trying to connect to target stm32wlx

I have an stlink-v2 hooked up to a newly designed PCB with an stm32wl55ccu7 but can't seem get OpenOCD working. It connects to the target but as soon as I try to connect with gdb, it segfaults due to a null pointer.

EDIT: I have also tried it out with a nucleo wl55jc1 with an stlink-v3 adapter, same error.

Any ideas?

~$ uname -a
Linux 32k 4.15.0-51-generic #55-Ubuntu SMP Wed May 15 14:27:21 UTC 2019 x86_64 x86_64 x86_64 GNU/Linux

~/OpenOCD $ > git rev-parse --short HEAD
ff701ce

Reading symbols from openocd...done.
(gdb) run
Starting program: /usr/local/bin/openocd -d3 -f interface/stlink.cfg -f target/stm32wlx.cfg
[Thread debugging using libthread_db enabled]
Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".
Open On-Chip Debugger 0.11.0-rc2+dev-00039-gff701ce82-dirty (2021-08-25-16:35)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
User : 13 1 options.c:63 configuration_output_handler(): debug_level: 3
User : 14 1 options.c:63 configuration_output_handler():
Debug: 15 1 options.c:244 add_default_dirs(): bindir=/usr/local/bin
Debug: 16 1 options.c:245 add_default_dirs(): pkgdatadir=/usr/local/share/openocd
Debug: 17 1 options.c:246 add_default_dirs(): exepath=/usr/local/bin
Debug: 18 1 options.c:247 add_default_dirs(): bin2data=../share/openocd
Debug: 19 1 configuration.c:42 add_script_search_dir(): adding /home/manne/.config/openocd
Debug: 20 1 configuration.c:42 add_script_search_dir(): adding /home/manne/.openocd
Debug: 21 1 configuration.c:42 add_script_search_dir(): adding /usr/local/bin/../share/openocd/site
Debug: 22 1 configuration.c:42 add_script_search_dir(): adding /usr/local/bin/../share/openocd/scripts
Debug: 23 1 configuration.c:97 find_file(): found /usr/local/bin/../share/openocd/scripts/interface/stlink.cfg
Debug: 24 1 command.c:146 script_debug(): command - adapter driver hla
Debug: 26 1 command.c:146 script_debug(): command - hla_layout stlink
Debug: 28 1 hla_interface.c:242 hl_interface_handle_layout_command(): hl_interface_handle_layout_command
Debug: 29 1 command.c:146 script_debug(): command - hla_device_desc ST-LINK
Debug: 31 1 hla_interface.c:216 hl_interface_handle_device_desc_command(): hl_interface_handle_device_desc_command
Debug: 32 1 command.c:146 script_debug(): command - hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753
Debug: 34 1 configuration.c:97 find_file(): found /usr/local/bin/../share/openocd/scripts/target/stm32wlx.cfg
Debug: 35 1 configuration.c:97 find_file(): found /usr/local/bin/../share/openocd/scripts/target/swj-dp.tcl
Debug: 36 1 command.c:146 script_debug(): command - transport select
Info : 37 1 transport.c:276 jim_transport_select(): auto-selecting first available session transport "hla_swd". To override use 'transport select '.
Debug: 38 1 hla_transport.c:205 hl_swd_transport_select(): hl_swd_transport_select
Debug: 39 1 configuration.c:97 find_file(): found /usr/local/bin/../share/openocd/scripts/mem_helper.tcl
Debug: 40 1 command.c:146 script_debug(): command - add_usage_text mrw address
Debug: 42 1 command.c:1115 help_add_command(): added 'mrw' help text
Debug: 43 1 command.c:146 script_debug(): command - add_help_text mrw Returns value of word in memory.
Debug: 45 1 command.c:1128 help_add_command(): added 'mrw' help text
Debug: 46 1 command.c:146 script_debug(): command - add_usage_text mrh address
Debug: 48 1 command.c:1115 help_add_command(): added 'mrh' help text
Debug: 49 1 command.c:146 script_debug(): command - add_help_text mrh Returns value of halfword in memory.
Debug: 51 1 command.c:1128 help_add_command(): added 'mrh' help text
Debug: 52 1 command.c:146 script_debug(): command - add_usage_text mrb address
Debug: 54 1 command.c:1115 help_add_command(): added 'mrb' help text
Debug: 55 1 command.c:146 script_debug(): command - add_help_text mrb Returns value of byte in memory.
Debug: 57 1 command.c:1128 help_add_command(): added 'mrb' help text
Debug: 58 1 command.c:146 script_debug(): command - add_usage_text mmw address setbits clearbits
Debug: 60 1 command.c:1115 help_add_command(): added 'mmw' help text
Debug: 61 1 command.c:146 script_debug(): command - add_help_text mmw Modify word in memory. new_val = (old_val & ~clearbits) | setbits;
Debug: 63 1 command.c:1128 help_add_command(): added 'mmw' help text
Debug: 64 1 command.c:146 script_debug(): command - transport select
Debug: 65 1 command.c:146 script_debug(): command - transport select
Debug: 66 1 command.c:146 script_debug(): command - transport select
Debug: 67 1 command.c:146 script_debug(): command - swd newdap stm32wlx cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x6ba02477
Debug: 68 1 hla_tcl.c:111 jim_hl_newtap_cmd(): Creating New Tap, Chip: stm32wlx, Tap: cpu, Dotted: stm32wlx.cpu, 8 params
Debug: 69 1 hla_tcl.c:121 jim_hl_newtap_cmd(): Processing option: -irlen
Debug: 70 1 hla_tcl.c:121 jim_hl_newtap_cmd(): Processing option: -ircapture
Debug: 71 1 hla_tcl.c:121 jim_hl_newtap_cmd(): Processing option: -irmask
Debug: 72 1 hla_tcl.c:121 jim_hl_newtap_cmd(): Processing option: -expected-id
Debug: 73 1 core.c:1488 jtag_tap_init(): Created Tap: stm32wlx.cpu @ abs position 0, irlen 0, capture: 0x0 mask: 0x0
Debug: 74 1 command.c:146 script_debug(): command - dap create stm32wlx.dap -chain-position stm32wlx.cpu
Debug: 75 1 command.c:146 script_debug(): command - transport select
Debug: 76 1 command.c:146 script_debug(): command - target create stm32wlx.m4 cortex_m -endian little -dap stm32wlx.dap
Info : 77 1 target.c:5657 target_create(): The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
Debug: 78 1 hla_target.c:203 adapter_target_create(): adapter_target_create
Debug: 79 1 hla_target.c:173 adapter_init_arch_info(): adapter_init_arch_info
Debug: 80 1 command.c:376 register_command(): command 'tpiu' is already registered in '' context
Debug: 81 1 command.c:376 register_command(): command 'rtt' is already registered in '' context
Debug: 82 1 command.c:146 script_debug(): command - stm32wlx.m4 configure -work-area-phys 0x20008000 -work-area-size 0x2000 -work-area-backup 0
Debug: 83 1 target.c:2161 target_free_all_working_areas_restore(): freeing all working areas
Debug: 84 1 target.c:2161 target_free_all_working_areas_restore(): freeing all working areas
Debug: 85 1 target.c:2161 target_free_all_working_areas_restore(): freeing all working areas
Debug: 86 1 command.c:146 script_debug(): command - flash bank stm32wlx.flash.m4 stm32l4x 0x08000000 0 0 0 stm32wlx.m4
Debug: 88 1 tcl.c:1319 handle_flash_bank_command(): 'stm32l4x' driver usage field missing
Debug: 89 1 command.c:146 script_debug(): command - flash bank stm32wlx.otp.m4 stm32l4x 0x1fff7000 0 0 0 stm32wlx.m4
Debug: 91 1 command.c:376 register_command(): command 'stm32l4x' is already registered in '' context
Debug: 92 1 command.c:376 register_command(): command 'lock' is already registered in 'stm32l4x' context
Debug: 93 1 command.c:376 register_command(): command 'unlock' is already registered in 'stm32l4x' context
Debug: 94 1 command.c:376 register_command(): command 'mass_erase' is already registered in 'stm32l4x' context
Debug: 95 1 command.c:376 register_command(): command 'option_read' is already registered in 'stm32l4x' context
Debug: 96 1 command.c:376 register_command(): command 'option_write' is already registered in 'stm32l4x' context
Debug: 97 1 command.c:376 register_command(): command 'trustzone' is already registered in 'stm32l4x' context
Debug: 98 1 command.c:376 register_command(): command 'wrp_desc' is already registered in 'stm32l4x' context
Debug: 99 1 command.c:376 register_command(): command 'option_load' is already registered in 'stm32l4x' context
Debug: 100 1 command.c:376 register_command(): command 'otp' is already registered in 'stm32l4x' context
Debug: 101 1 tcl.c:1319 handle_flash_bank_command(): 'stm32l4x' driver usage field missing
Debug: 102 1 command.c:146 script_debug(): command - targets stm32wlx.m4
Debug: 104 1 command.c:146 script_debug(): command - adapter speed 500
Debug: 106 1 core.c:1822 jtag_config_khz(): handle jtag khz
Debug: 107 1 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 108 1 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 109 1 command.c:146 script_debug(): command - adapter srst delay 100
Debug: 111 1 command.c:146 script_debug(): command - transport select
Debug: 112 1 command.c:146 script_debug(): command - reset_config srst_nogate
Debug: 114 1 command.c:146 script_debug(): command - transport select
Debug: 115 1 command.c:146 script_debug(): command - stm32wlx.m4 configure -event reset-init
# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
# Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
# 2 WS compliant with VOS=Range1 and 24 MHz.
mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTEN | 2(Latency)
mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz
# Boost JTAG frequency
adapter speed 4000

Debug: 116 1 command.c:146 script_debug(): command - stm32wlx.m4 configure -event reset-start
# Reset clock is MSI (4 MHz)
adapter speed 500

Debug: 117 1 command.c:146 script_debug(): command - stm32wlx.m4 configure -event examine-end
global _DUALCORE
global _CHIPNAME

# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0

# Stop watchdog counters during halt
# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE004203C 0x00001800 0

if { [set _DUALCORE] } {
	targets $_CHIPNAME.m4

	# enable CPU2 boot after reset and after wakeup from Stop or Standby mode
	# PWR_CR4 |= C2BOOT
	mmw 0x5800040C 0x00008000 0
}

Debug: 118 1 command.c:146 script_debug(): command - stm32wlx.m4 configure -event trace-config
# nothing to do

Info : 119 1 server.c:312 add_service(): Listening on port 6666 for tcl connections
Info : 120 1 server.c:312 add_service(): Listening on port 4444 for telnet connections
Debug: 121 1 command.c:146 script_debug(): command - init
Debug: 123 1 command.c:146 script_debug(): command - target init
Debug: 125 1 command.c:146 script_debug(): command - target names
Debug: 126 1 command.c:146 script_debug(): command - stm32wlx.m4 cget -event gdb-flash-erase-start
Debug: 127 1 command.c:146 script_debug(): command - stm32wlx.m4 configure -event gdb-flash-erase-start reset init
Debug: 128 1 command.c:146 script_debug(): command - stm32wlx.m4 cget -event gdb-flash-write-end
Debug: 129 1 command.c:146 script_debug(): command - stm32wlx.m4 configure -event gdb-flash-write-end reset halt
Debug: 130 1 command.c:146 script_debug(): command - stm32wlx.m4 cget -event gdb-attach
Debug: 131 1 command.c:146 script_debug(): command - stm32wlx.m4 configure -event gdb-attach halt 1000
Debug: 132 1 target.c:1628 handle_target_init_command(): Initializing targets...
Debug: 133 1 hla_target.c:193 adapter_init_target(): adapter_init_target
Debug: 134 1 semihosting_common.c:99 semihosting_common_init():
Debug: 135 2 hla_interface.c:109 hl_interface_init(): hl_interface_init
Debug: 136 2 hla_layout.c:95 hl_layout_init(): hl_layout_init
Debug: 137 2 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 138 2 core.c:1789 adapter_khz_to_speed(): have interface set up
Debug: 139 2 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 140 2 core.c:1789 adapter_khz_to_speed(): have interface set up
Info : 141 2 core.c:1565 adapter_init(): clock speed 500 kHz
Debug: 142 2 openocd.c:144 handle_init_command(): Debug Adapter init complete
Debug: 143 2 command.c:146 script_debug(): command - transport init
Debug: 145 2 transport.c:229 handle_transport_init(): handle_transport_init
Debug: 146 2 hla_transport.c:156 hl_transport_init(): hl_transport_init
Debug: 147 2 hla_transport.c:173 hl_transport_init(): current transport hla_swd
Debug: 148 2 hla_interface.c:42 hl_interface_open(): hl_interface_open
Debug: 149 2 hla_layout.c:40 hl_layout_open(): hl_layout_open
Debug: 150 2 stlink_usb.c:3542 stlink_open(): stlink_open
Debug: 151 2 stlink_usb.c:3556 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3744 serial:
Debug: 152 2 stlink_usb.c:3556 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3748 serial:
Debug: 153 2 stlink_usb.c:3556 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374b serial:
Debug: 154 2 stlink_usb.c:3556 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374d serial:
Debug: 155 2 stlink_usb.c:3556 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374e serial:
Debug: 156 2 stlink_usb.c:3556 stlink_open(): transport: 4 vid: 0x0483 pid: 0x374f serial:
Debug: 157 2 stlink_usb.c:3556 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3752 serial:
Debug: 158 2 stlink_usb.c:3556 stlink_open(): transport: 4 vid: 0x0483 pid: 0x3753 serial:
[New Thread 0x7ffff6743700 (LWP 20785)]
Info : 159 4 stlink_usb.c:1346 stlink_usb_version(): STLINK V2J29S7 (API v2) VID:PID 0483:3748
Debug: 160 4 stlink_usb.c:1567 stlink_usb_exit_mode(): MODE: 0x02
Info : 161 5 stlink_usb.c:1378 stlink_usb_check_voltage(): Target voltage: 3.151562
Debug: 162 5 stlink_usb.c:1635 stlink_usb_init_mode(): MODE: 0x01
Debug: 163 5 stlink_usb.c:2956 stlink_dump_speed_map(): Supported clock speeds are:
Debug: 164 5 stlink_usb.c:2959 stlink_dump_speed_map(): 4000 kHz
Debug: 165 5 stlink_usb.c:2959 stlink_dump_speed_map(): 1800 kHz
Debug: 166 5 stlink_usb.c:2959 stlink_dump_speed_map(): 1200 kHz
Debug: 167 5 stlink_usb.c:2959 stlink_dump_speed_map(): 950 kHz
Debug: 168 5 stlink_usb.c:2959 stlink_dump_speed_map(): 480 kHz
Debug: 169 5 stlink_usb.c:2959 stlink_dump_speed_map(): 240 kHz
Debug: 170 5 stlink_usb.c:2959 stlink_dump_speed_map(): 125 kHz
Debug: 171 5 stlink_usb.c:2959 stlink_dump_speed_map(): 100 kHz
Debug: 172 5 stlink_usb.c:2959 stlink_dump_speed_map(): 50 kHz
Debug: 173 5 stlink_usb.c:2959 stlink_dump_speed_map(): 25 kHz
Debug: 174 5 stlink_usb.c:2959 stlink_dump_speed_map(): 15 kHz
Debug: 175 5 stlink_usb.c:2959 stlink_dump_speed_map(): 5 kHz
Debug: 176 8 stlink_usb.c:1694 stlink_usb_init_mode(): MODE: 0x02
Debug: 177 8 stlink_usb.c:3886 stlink_usb_open_ap(): AP 0 enabled
Debug: 178 9 stlink_usb.c:3629 stlink_open(): Using TAR autoincrement: 4096
Debug: 179 9 core.c:640 adapter_system_reset(): SRST line released
Debug: 180 111 hla_interface.c:67 hl_interface_init_target(): hl_interface_init_target
Debug: 181 111 stlink_usb.c:1927 stlink_usb_idcode(): IDCODE: 0x6BA02477
Debug: 182 111 command.c:146 script_debug(): command - dap init
Debug: 184 111 arm_dap.c:106 dap_init_all(): Initializing all DAPs ...
Debug: 185 111 openocd.c:161 handle_init_command(): Examining targets...
Debug: 186 111 target.c:1816 target_call_event_callbacks(): target event 19 (examine-start) for core stm32wlx.m4
Debug: 187 111 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe000ed00 4 1
Debug: 188 112 target.c:2578 target_read_u32(): address: 0xe000ed00, value: 0x410fc241
Debug: 189 112 cortex_m.c:2039 cortex_m_examine(): Cortex-M4 r0p1 processor detected
Debug: 190 112 cortex_m.c:2050 cortex_m_examine(): cpuid: 0x410fc241
Debug: 191 112 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe000ef40 4 1
Debug: 192 113 target.c:2578 target_read_u32(): address: 0xe000ef40, value: 0x00000000
Debug: 193 113 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe000ef44 4 1
Debug: 194 113 target.c:2578 target_read_u32(): address: 0xe000ef44, value: 0x00000000
Debug: 195 113 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe000edf0 4 1
Debug: 196 114 target.c:2578 target_read_u32(): address: 0xe000edf0, value: 0x00030003
Debug: 197 114 target.c:2666 target_write_u32(): address: 0xe000edfc, value: 0x01000000
Debug: 198 114 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe000edfc 4 1
Debug: 199 115 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe0002000 4 1
Debug: 200 116 target.c:2578 target_read_u32(): address: 0xe0002000, value: 0x00000260
Debug: 201 116 target.c:2666 target_write_u32(): address: 0xe0002008, value: 0x00000000
Debug: 202 116 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0002008 4 1
Debug: 203 117 target.c:2666 target_write_u32(): address: 0xe000200c, value: 0x00000000
Debug: 204 117 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe000200c 4 1
Debug: 205 117 target.c:2666 target_write_u32(): address: 0xe0002010, value: 0x00000000
Debug: 206 117 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0002010 4 1
Debug: 207 118 target.c:2666 target_write_u32(): address: 0xe0002014, value: 0x00000000
Debug: 208 118 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0002014 4 1
Debug: 209 119 target.c:2666 target_write_u32(): address: 0xe0002018, value: 0x00000000
Debug: 210 119 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0002018 4 1
Debug: 211 120 target.c:2666 target_write_u32(): address: 0xe000201c, value: 0x00000000
Debug: 212 120 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe000201c 4 1
Debug: 213 120 target.c:2666 target_write_u32(): address: 0xe0002020, value: 0x00000000
Debug: 214 120 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0002020 4 1
Debug: 215 121 target.c:2666 target_write_u32(): address: 0xe0002024, value: 0x00000000
Debug: 216 121 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0002024 4 1
Debug: 217 122 cortex_m.c:2150 cortex_m_examine(): FPB fpcr 0x260, numcode 6, numlit 2
Debug: 218 122 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe0001000 4 1
Debug: 219 123 target.c:2578 target_read_u32(): address: 0xe0001000, value: 0x40000000
Debug: 220 123 cortex_m.c:1868 cortex_m_dwt_setup(): DWT_CTRL: 0x40000000
Debug: 221 123 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe0001fbc 4 1
Debug: 222 124 target.c:2578 target_read_u32(): address: 0xe0001fbc, value: 0x00000000
Debug: 223 124 cortex_m.c:1875 cortex_m_dwt_setup(): DWT_DEVARCH: 0x0
Debug: 224 124 target.c:2666 target_write_u32(): address: 0xe0001028, value: 0x00000000
Debug: 225 124 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0001028 4 1
Debug: 226 124 target.c:2666 target_write_u32(): address: 0xe0001038, value: 0x00000000
Debug: 227 124 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0001038 4 1
Debug: 228 125 target.c:2666 target_write_u32(): address: 0xe0001048, value: 0x00000000
Debug: 229 125 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0001048 4 1
Debug: 230 126 target.c:2666 target_write_u32(): address: 0xe0001058, value: 0x00000000
Debug: 231 126 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0001058 4 1
Debug: 232 127 cortex_m.c:1924 cortex_m_dwt_setup(): DWT dwtcr 0x40000000, comp 4, watch/trigger
Info : 233 127 cortex_m.c:2160 cortex_m_examine(): stm32wlx.m4: hardware has 6 breakpoints, 4 watchpoints
Debug: 234 127 target.c:1816 target_call_event_callbacks(): target event 21 (examine-end) for core stm32wlx.m4
Debug: 235 127 target.c:4768 target_handle_event(): target(0): stm32wlx.m4 (hla_target) event: 21 (examine-end) action:
global _DUALCORE
global _CHIPNAME

# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0

# Stop watchdog counters during halt
# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE004203C 0x00001800 0

if { [set _DUALCORE] } {
	targets $_CHIPNAME.m4

	# enable CPU2 boot after reset and after wakeup from Stop or Standby mode
	# PWR_CR4 |= C2BOOT
	mmw 0x5800040C 0x00008000 0
}

Debug: 236 127 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe0042004 4 1
Debug: 237 128 command.c:146 script_debug(): command - mww 0xE0042004 7
Debug: 238 128 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 239 129 target.c:2578 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 240 130 armv7m.c:371 armv7m_read_core_reg(): read r0 value 0x00001800
Debug: 241 131 armv7m.c:371 armv7m_read_core_reg(): read r1 value 0x00000000
Debug: 242 132 armv7m.c:371 armv7m_read_core_reg(): read r2 value 0x006000d0
Debug: 243 133 armv7m.c:371 armv7m_read_core_reg(): read r3 value 0x00d00000
Debug: 244 134 armv7m.c:371 armv7m_read_core_reg(): read r4 value 0x40020000
Debug: 245 134 armv7m.c:371 armv7m_read_core_reg(): read r5 value 0x58000038
Debug: 246 135 armv7m.c:371 armv7m_read_core_reg(): read r6 value 0x40013000
Debug: 247 136 armv7m.c:371 armv7m_read_core_reg(): read r7 value 0x00000000
Debug: 248 137 armv7m.c:371 armv7m_read_core_reg(): read r8 value 0x00000000
Debug: 249 138 armv7m.c:371 armv7m_read_core_reg(): read r9 value 0x00000000
Debug: 250 139 armv7m.c:371 armv7m_read_core_reg(): read r10 value 0x00000000
Debug: 251 140 armv7m.c:371 armv7m_read_core_reg(): read r11 value 0x00000000
Debug: 252 141 armv7m.c:371 armv7m_read_core_reg(): read r12 value 0x80000000
Debug: 253 141 armv7m.c:371 armv7m_read_core_reg(): read sp value 0x200014f0
Debug: 254 142 armv7m.c:371 armv7m_read_core_reg(): read lr value 0x1fff2b45
Debug: 255 143 armv7m.c:371 armv7m_read_core_reg(): read pc value 0x1fff246a
Debug: 256 144 armv7m.c:371 armv7m_read_core_reg(): read xPSR value 0x41000000
Debug: 257 145 armv7m.c:371 armv7m_read_core_reg(): read msp value 0x200014f0
Debug: 258 146 armv7m.c:371 armv7m_read_core_reg(): read psp value 0x00000000
Debug: 259 147 armv7m.c:371 armv7m_read_core_reg(): read pmsk_bpri_fltmsk_ctrl value 0x00000000
Debug: 260 148 armv7m.c:371 armv7m_read_core_reg(): read msp_ns value 0x41000000
Debug: 261 148 armv7m.c:371 armv7m_read_core_reg(): read psp_ns value 0x200014f0
Debug: 262 149 armv7m.c:371 armv7m_read_core_reg(): read msp_s value 0x00000000
Debug: 263 150 armv7m.c:371 armv7m_read_core_reg(): read psp_s value 0x00000000
Debug: 264 151 armv7m.c:371 armv7m_read_core_reg(): read msplim_s value 0x00000000
Debug: 265 152 armv7m.c:371 armv7m_read_core_reg(): read psplim_s value 0x200014f0
Debug: 266 153 armv7m.c:371 armv7m_read_core_reg(): read msplim_ns value 0x00000000
Debug: 267 154 armv7m.c:371 armv7m_read_core_reg(): read psplim_ns value 0x00000000
Debug: 268 155 armv7m.c:371 armv7m_read_core_reg(): read pmsk_bpri_fltmsk_ctrl_s value 0x00000000
Debug: 269 155 armv7m.c:371 armv7m_read_core_reg(): read pmsk_bpri_fltmsk_ctrl_ns value 0x00000000
Debug: 270 157 armv7m.c:369 armv7m_read_core_reg(): read d0 value 0x0000000000000000
Debug: 271 159 armv7m.c:369 armv7m_read_core_reg(): read d1 value 0x0000000000000000
Debug: 272 161 armv7m.c:369 armv7m_read_core_reg(): read d2 value 0x0000000000000000
Debug: 273 162 armv7m.c:369 armv7m_read_core_reg(): read d3 value 0x0000000000000000
Debug: 274 164 armv7m.c:369 armv7m_read_core_reg(): read d4 value 0x0000000000000000
Debug: 275 166 armv7m.c:369 armv7m_read_core_reg(): read d5 value 0x0000000000000000
Debug: 276 167 armv7m.c:369 armv7m_read_core_reg(): read d6 value 0x0000000000000000
Debug: 277 169 armv7m.c:369 armv7m_read_core_reg(): read d7 value 0x0000000000000000
Debug: 278 171 armv7m.c:369 armv7m_read_core_reg(): read d8 value 0x0000000000000000
Debug: 279 173 armv7m.c:369 armv7m_read_core_reg(): read d9 value 0x0000000000000000
Debug: 280 174 armv7m.c:369 armv7m_read_core_reg(): read d10 value 0x0000000000000000
Debug: 281 176 armv7m.c:369 armv7m_read_core_reg(): read d11 value 0x0000000000000000
Debug: 282 178 armv7m.c:369 armv7m_read_core_reg(): read d12 value 0x0000000000000000
Debug: 283 180 armv7m.c:369 armv7m_read_core_reg(): read d13 value 0x0000000000000000
Debug: 284 181 armv7m.c:369 armv7m_read_core_reg(): read d14 value 0x0000000000000000
Debug: 285 183 armv7m.c:369 armv7m_read_core_reg(): read d15 value 0x0000000000000000
Debug: 286 184 armv7m.c:371 armv7m_read_core_reg(): read fpscr value 0x00000000
Debug: 287 185 hla_target.c:289 adapter_debug_entry(): entered debug state in core mode: Thread at PC 0x1fff246a, target->state: halted
Debug: 288 185 target.c:1816 target_call_event_callbacks(): target event 0 (gdb-halt) for core stm32wlx.m4
Debug: 289 185 target.c:1816 target_call_event_callbacks(): target event 1 (halted) for core stm32wlx.m4
Debug: 290 185 hla_target.c:331 adapter_poll(): halted: PC: 0x1fff246a
Debug: 292 185 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe0042004 4 1
Debug: 293 186 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe004203c 4 1
Debug: 294 187 command.c:146 script_debug(): command - mww 0xE004203C 6144
Debug: 296 188 hla_target.c:618 adapter_write_memory(): adapter_write_memory 0xe004203c 4 1
Debug: 297 189 command.c:146 script_debug(): command - flash init
Debug: 299 190 tcl.c:1385 handle_flash_init_command(): Initializing flash devices...
Debug: 300 190 command.c:146 script_debug(): command - nand init
Debug: 302 190 tcl.c:498 handle_nand_init_command(): Initializing NAND devices...
Debug: 303 191 command.c:146 script_debug(): command - pld init
Debug: 305 191 pld.c:206 handle_pld_init_command(): Initializing PLDs...
Debug: 306 191 command.c:146 script_debug(): command - tpiu init
Info : 307 191 gdb_server.c:3503 gdb_target_start(): starting gdb server for stm32wlx.m4 on 3333
Info : 308 191 server.c:312 add_service(): Listening on port 3333 for gdb connections
Info : 309 6059 server.c:100 add_connection(): accepting 'gdb' connection on tcp/3333
Debug: 310 6059 breakpoints.c:384 breakpoint_clear_target_internal(): Delete all breakpoints for target: stm32wlx.m4
Debug: 311 6059 breakpoints.c:524 watchpoint_clear_target(): Delete all watchpoints for target: stm32wlx.m4
Debug: 312 6059 target.c:1816 target_call_event_callbacks(): target event 22 (gdb-attach) for core stm32wlx.m4
Debug: 313 6059 target.c:4768 target_handle_event(): target(0): stm32wlx.m4 (hla_target) event: 22 (gdb-attach) action: halt 1000
Debug: 314 6059 command.c:146 script_debug(): command - halt 1000
Debug: 316 6060 target.c:3249 handle_halt_command(): -
Debug: 317 6060 hla_target.c:418 adapter_halt(): adapter_halt
Debug: 318 6060 hla_target.c:421 adapter_halt(): target was already halted
Debug: 319 6060 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0xe0042000 4 1
Debug: 320 6061 target.c:2578 target_read_u32(): address: 0xe0042000, value: 0x10016497
Info : 321 6061 stm32l4x.c:1643 stm32l4_probe(): device idcode = 0x10016497 (STM32WLEx/WL5x - Rev 1.1 : 0x1001)
Debug: 322 6061 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0x58004020 4 1
Debug: 323 6062 target.c:2578 target_read_u32(): address: 0x58004020, value: 0x3ffff0aa
Info : 324 6062 stm32l4x.c:1659 stm32l4_probe(): RDP level 0 (0xAA)
Debug: 325 6062 hla_target.c:603 adapter_read_memory(): adapter_read_memory 0x1fff75e0 2 1
Debug: 326 6063 target.c:2602 target_read_u16(): address: 0x1fff75e0, value: 0x0100
Info : 327 6063 stm32l4x.c:1702 stm32l4_probe(): flash size = 256kbytes

Thread 1 "openocd" received signal SIGSEGV, Segmentation fault.
0x00005555556b38e9 in stm32l4_probe (bank=0x555555c59390) at src/flash/nor/stm32l4x.c:1861
1861 if (armv7m->debug_ap->ap_num == 1)
(gdb) bt
#0 0x00005555556b38e9 in stm32l4_probe (bank=0x555555c59390) at src/flash/nor/stm32l4x.c:1861
#1 0x00005555556b3d78 in stm32l4_auto_probe (bank=0x555555c59390) at src/flash/nor/stm32l4x.c:1946
#2 0x00005555555f2597 in get_flash_bank_by_num (num=0, bank=0x7fffffffdde0) at src/flash/nor/core.c:299
#3 0x0000555555626a27 in gdb_new_connection (connection=0x555555c777e0) at src/server/gdb_server.c:1004
#4 0x000055555562e056 in add_connection (service=0x555555c73f80, cmd_ctx=0x555555c07260) at src/server/server.c:101
#5 0x000055555562f1ae in server_loop (command_context=0x555555c07260) at src/server/server.c:543
#6 0x00005555555ad3fd in openocd_thread (argc=6, argv=0x7fffffffe0e8, cmd_ctx=0x555555c07260) at src/openocd.c:318
#7 0x00005555555ad4fa in openocd_main (argc=6, argv=0x7fffffffe0e8) at src/openocd.c:360
#8 0x00005555555acda6 in main (argc=6, argv=0x7fffffffe0e8) at src/main.c:39
(gdb) quit

EDIT: debug_ap is null, which ultimately causes the segfault.

STM32F769 Not reading from D-Cache

The latest build does not appear to be reading values from the D-Cache on Cortex-M7

The mainstream OpenOCD 0.11.0 works

Build fails in branch openocd-cubeide-r4 or tag openocd-cubeide-v1.8.0 or later [-Werror=maybe-uninitialized]

Build fails in fresh docker build on branch openocd-cubeide-r4 or tag openocd-cubeide-v1.8.0 or later.
Tag openocd-cubeide-v1.7.0 and branch openocd-cubeide-r3 build fine.

Docker commands:

ARG VARIANT="focal"
FROM ubuntu:${VARIANT} AS openocd-builder

ARG OPENOCD_PATH=/opt/openocd-stm

RUN apt-get update && export DEBIAN_FRONTEND=noninteractive \
    && apt-get -y install --no-install-recommends \
    build-essential \
    ca-certificates \
    git \
    # build tools for openocd
    libhidapi-dev \
    libusb-1.0-0-dev \
    libusb-dev \
    libtool \ 
    make \
    automake \
    autoconf \
    pkg-config \
    tclsh \
    telnet \
 && rm -rf /var/lib/apt/lists/*

RUN git clone --branch openocd-cubeide-r4 https://github.com/STMicroelectronics/OpenOCD.git ${OPENOCD_PATH} \
 && cd ${OPENOCD_PATH} \
 && ./bootstrap \
 && ./configure --enable-stlink \
 && make -j"$($(nproc) + 2)"

Full error message:

#6 67.64 /bin/bash ./libtool  --tag=CC   --mode=link gcc -Wall -Wstrict-prototypes -Wformat-security -Wshadow -Wextra -Wno-unused-parameter -Wbad-function-cast -Wcast-align -Wredundant-decls -Wpointer-arith -Wundef -Wno-error=deprecated-declarations -Werror -g -O2   -o src/target/openrisc/libopenrisc.la  src/target/openrisc/or1k.lo src/target/openrisc/or1k_du_adv.lo src/target/openrisc/or1k_tap_mohor.lo src/target/openrisc/or1k_tap_vjtag.lo src/target/openrisc/or1k_tap_xilinx_bscan.lo src/target/openrisc/jsp_server.lo  -lutil -ldl
#6 67.71 In file included from ./src/helper/list.h:21,
#6 67.71                  from ./src/helper/binarybuffer.h:25,
#6 67.71                  from src/jtag/drivers/stlink_usb.c:37:
#6 67.71 src/jtag/drivers/stlink_usb.c: In function 'stlink_dap_op_queue_run_internal':
#6 67.71 mv -f src/target/.deps/libtarget_la-armv8_dpm.Tpo src/target/.deps/libtarget_la-armv8_dpm.Plo
#6 67.74 ./src/helper/types.h:194:9: error: 'misc_items' may be used uninitialized in this function [-Werror=maybe-uninitialized]
#6 67.74   194 |  buf[0] = (uint8_t) (val >> 0);
#6 67.74       |  ~~~~~~~^~~~~~~~~~~~~~~~~~~~~~
#6 67.74 src/jtag/drivers/stlink_usb.c:4595:20: note: 'misc_items' was declared here
#6 67.74  4595 |  unsigned int cnt, misc_items;
#6 67.74       |                    ^~~~~~~~~~

gdbserver, Failed to read memory at 0xfffffffe

Any idea what is going wrong?

Development board : stm32h7a3zi-q

openocd.cfg :

source [find interface/stlink-dap.cfg]
transport select dapdirect_swd

set WORKAREASIZE 0x3000
set CHIPNAME STM32H7A3ZI
set BOARDNAME NUCLEO-H7A3ZI_Q

source [find target/stm32h7x.cfg]

# Use connect_assert_srst here to be able to program
# even when core is in sleep mode
reset_config srst_only srst_nogate connect_assert_srst

$_CHIPNAME.cpu0 configure -event gdb-attach {
        echo "Debugger attaching: halting execution"
        gdb_breakpoint_override hard
}

$_CHIPNAME.cpu0 configure -event gdb-detach {
        echo "Debugger detaching: resuming execution"
        resume
}

# Due to the use of connect_assert_srst, running gdb requires
# to reset halt just after openocd init.
rename init old_init
proc init {} {
        old_init
        reset halt
}

openocd runtime info :

Open On-Chip Debugger 0.11.0+dev-00242-g7036ed509-dirty (2021-09-20-14:06)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
init
Info : STLINK V3J8M3 (API v3) VID:PID 0483:374E
Info : stlink_dap_op_connect(connect)
Info : SWD DPIDR 0x6ba02477
Info : STM32H7A3ZI.cpu0: hardware has 8 breakpoints, 4 watchpoints
Info : STM32H7A3ZI.cpu0: external reset detected
Info : gdb port disabled
Info : starting gdb server for STM32H7A3ZI.cpu0 on 3333
Info : Listening on port 3333 for gdb connections
target halted due to debug-request, current mode: Thread 
xPSR: 0x01000000 pc: 0x08001530 msp: 0x24000700
    TargetName         Type       Endian TapName            State       
--  ------------------ ---------- ------ ------------------ ------------
 0  STM32H7A3ZI.ap2    mem_ap     little STM32H7A3ZI.cpu    halted
 1* STM32H7A3ZI.cpu0   cortex_m   little STM32H7A3ZI.cpu    halted

target halted due to debug-request, current mode: Thread 
xPSR: 0x01000000 pc: 0x08001530 msp: 0x24000700
Info : Listening on port 6333 for tcl connections
Info : Listening on port 4444 for telnet connections
target halted due to debug-request, current mode: Thread 
xPSR: 0x01000000 pc: 0x08001530 msp: 0x24000700
Info : accepting 'gdb' connection on tcp/3333
Debugger attaching: halting execution
force hard breakpoints
Info : Device: STM32H7Ax/7Bx
Info : flash size probed value 2048
Info : STM32H7 flash has dual banks
Info : Bank (0) size is 1024 kb, base address is 0x08000000
Info : New GDB Connection: 1, Target STM32H7A3ZI.cpu0, state: halted
Error: Failed to read memory at 0xfffffffe

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stmicroelectronics / openocd Goto Github PK

openocd's Introduction

STMicroelectronics/OpenOCD

1. Overview

2. Contributing guide

Before opening an issue

Pull Requests

openocd's People

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openocd's Issues

Issue

Environment

Board

Windows 10

STLink-V3

STM32CubeIDE

OpenOCD

STM32CubeIDE Plugin

xPack OpenOCD

Official

Generated OpenOCD Config File

Outputs

OpenOCD (STM32CubeIDE Plugin)

Debug Level 3

Debug Level 0

xPack OpenOCD

openocd.cfg :

openocd runtime info :

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