steffenreith / j1sc Goto Github PK

@SteffenReith, you said that you are developing the devel branch on the Mac M1. Which means that you have the simulator running on the M1 Mac.

I did not find any instructions on how to do that. It just said load some drivers for Linux.

So how do I get the simulation working on the M1 Mac?

In my news, I did manage to create a much simplified PicoIce.scala board using the devel branch. It compiles but does not run. But I am getting more familiar with all of these libraries.

There are many files in J1Sc/src/main/scala defining the circuit. This documentation is an overview of what those files do. For simplicity I deleted the .scala from the file names.

J1: This is the highest level of the J1, defining interfaces to the outside.
J1Core: Defines signals towards the inner part of the J1.

INNER WORLD

J1Stack: Basic stack definitions and logic.

J1RStack: Return stack definition and logic, all in one place.

J1DStack: Data stack definition and logic.

J1Decoder: Decides the instruction. Just decides if it is a literal, call, jump,
conditional jump or instruction.

MainMemory: Defines the main memory assuming multiple smaller blocks (???)

J1PC: Program counter

Timer: Sets alarms

J1Alu: Does the basic operations (Words).

J1Bus: I think that there are multiple busses, but I am not yet sure. One for the LEDs, one for the GPIO, PWM, LEDs, and SSD.
J1BusSlaveFactory:

OUTER WORLD

DBPinArray: debounced Pin array. Input Pins, Debounced Pins, a timer, and some kind of bus.

GPIO: Define the GPIOs. Assumes that we are using PMODs.

LEDArray: A register of LED values which you can read and write to. Why does in mention PWM?

InterruptCtrl: Defines the interrupts. I did not fully understand this part.

PWM: Pulse Width Modulation is for control of motors. The width has to be a power of 2.

SSD: For driving a Solid State Drive.

JTAG FOR SINGLE STEP DEBUGGING

J1Jtag:
J1JtagData:
SingleStepUnit:

Board Definitions

Here is where you customize things.

J1Config: Configure IRQ, JTAG. Timer, Instruction set and the J1 itself. Includes instruction set tests.
CoreConfig.: Configure UART, LEDs, PWM, and GPIO for various boards.


*J1Ice.**: Define a J1 for the Ice Board. J1Ico Define a J1 for the Ico board.

J1Nexys4X: Define a J1 for the Nexys4X board.

If you like this I can create a pull request.

So I flashed a blinky onto my pico-ice board using SpinalHDL and apio. Hurrah. Now I am trying to synthesize the J1SC for the Pico-Ice board. Oh boy, it is quite tricky. There is a lot of stuff in there.

What Mecrisp did is to creae a directory skeletalstructure which just had the core parts in it. It was easy to get it up and running, and then one could add things back in one at a time.

Your code has LED arrays, button arrays, a uart led, a pwm led, interrupts, bridges, a clock lock, and who knows what else.

It takes a while to read all of the code, figure out what they all do, and figure out how to turn them off.

The problem is that it is lots of changes, and then at the end of the day, when everything is not working, I will not know what I broke. The ideal is to make it easy to get the first version working on an FPGA.

As a software developer, I would always make lots of changes and then debug it. As an FPGA developer, they repeatedly instruct us to make one change at a time, get it to work, and then make the next change.

I am not asking that you do anything, I am just recording what might make life easier for those who follow in my footsteps.

First thank you for creating this repository.

I plan on using this to generate many core Forth processors.
You can read more about my plans here.
https://forth.pythonlinks.info

Probably initially as an audio synthesizer. There are a bunch of us interested in audio synthesis on the pico-ice discord server.

You may have seen my SVFIG talk on "A review of Forth Soft Core Processors"

https://www.youtube.com/watch?v=qgmrZoJyHUw

More recently I did the same talk at the Stockholm FPGA conference. Here are the updated slides.
https://pythonlinks.info/presentations/StockholmConference.pdf

It turns out that the Mecrisp Forth interpreter is 200 times smaller than the Python interpreter. Wow.

I recently bought the Pico-Ice and the Upduino FPGA boards. I released an echo server for the Pico-Ice.
https://forth.pythonlinks.info/pico-ice-echo-server

Then I got Mecrisp Forth running on the Pico-Ice. But it took up
way too many resources.
ICESTORM_LC: 2604/ 5280 49%

Hard to buld a many core, when half the luts are already used.

But there is a more important reason to switch to this software stack. If you look at the Mecrisp source code, it support some 12 boards, and 28 different options in the verilog files. Really hard to mange that complexity in pure Verilog. Much better to do it in a high level language.

I took a look at MyHDL, did not like it. They generate the code, but throw out hierarchy information at simulation time, making debugging harder. Amaranth did not resonate with me either. I took one look at SpinalHDL, and everything looks very reasonable, even fantastic. I can refer to something in another branch of the hierarchy without having to manage wires up and down the stack. Awesome.

Not only I think so. The VexRiscV which won the first prize at the RISC-V Summit softCore contest, was also written in SpinalHDL

https://tomverbeure.github.io/rtl/2018/12/06/The-VexRiscV-CPU-A-New-Way-To-Design.html

Also I think it is much better to start with a tiny core, and only add in the stuff that I need.

As for issues, I wish that there were a newer release of this software, and I wish that more Electrical Engineers were aware of the advantages of high level languages, and were using this software, instead of sticking to Verilog and VHDL. Oh well.

Wish me luck.

I tried installing JDK 8, but could not find it on the web. They redirect to JDK version 21. So I installed that. I hope it all works.