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KVS_HDL

A minimal implementation for CPU-less Key-Value Store on FPGA. See Spec and Design.

Simulation on OSX

$ brew install icarus-verilog gtkwave
$ cd cores/kvs/test
$ make
$ make wave

Supported FPGA board

Sources

/boards/ecp3versa/synthesis           -- project files
/boards/ecp3versa/rtl/kvs_hdl_top.v   -- top module
/cores/crc32/rtl/crc32.v              -- generate ethernet FCS
/cores/crc16/rtl/crc16.v              -- generate hashkey
/cores/kvs/rtl/kvs.v                  -- Key-Value Store module

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