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License: GNU General Public License v3.0
A New 8-Bit Architecture
License: GNU General Public License v3.0
I'm being purposefully broad here. It seems to be quite a big omission. There's no way to arbitrarily index an array only increment and decrement.
It can be solved either with an ADD/SUB BC, DD/EE/#N/#NN or with an LDA (BC±DD/EE/N/NN)
I realize there's no space for all 16 of the opcodes, but you really only need 2 or 4 of those.
Hello.
I noticed that, while eight different instructions are listed regarding the shadow registers on the Opcode Breakdown sheet of the document, only two are documented in the ISA sheet. Is there any reason for this omission, or were they simply forgotten? And what mnemonics will be used for them? The load and store A to (DD) instructions could be simply written as LDA (DD)
or STA (DD)
, but would the increment and decrement DD or EE instructions be written as INCD DECD INCE DECE
or in some other manner?
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