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five-stage-pipelined-cpu-final-project-verilog's Introduction

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Hello
My name is Shiv Patel

About me:

  • CS Student at The Pennsylvania State University
    • Minors in Math, Astrophysics and Planetary Science
  • Currently a Research Assistant with the McEntaffer Rocket Group at Penn state
    • My main focus is on the telemetry system as well as data processing
  • In my free time, I spend most of time doing Photography.
  • Connect with me on LinkedIn

🛠️ Languages and Tools :

C++

GitHub

Java

docker

Linux

Python

Bash

SystemVerilog

Swift


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