shaybarak / tomasulo Goto Github PK

This is simulated, but assuming it can be done "for free" in parallel to handling the L2 miss with no extra cycle penalty. When L1 blocks are thrown in that manner, they are only marked as not valid, they aren't overwritten and therefore the old data remains in the data memories (and is written to the dump files).

For trace

(obviously we still have to wait until that block is present)

The write will be processed in the background (hits as well as misses), while allowing other arithmetic commands to execute in the CPU in parallel. On the next L1 data cache access, we first wait for the background write to complete, if it hasn't already, then we handle the new cache access (which may itself return early and be processed in the background if it's a new write).

Loading should be cyclic within L1 block and within the remaining L2 block.

The L1 data cache has a single word buffer for handling write misses in the background.
On the next L1 data cache access, we first wait for the background write to complete, if it hasn't already, then we handle the new cache access (which may itself return early and be processed in the background if it's a new write).

As per Gdalia's forum reply.

According to Gdalia's reply.

Changed methods to use default values.
However, since way is the only one passed with default value, it must be the last parameter, so i switched the order of way and offset.
Since offset and way are from same type, if we do not change order, code will compile and we will have silent bug (bob).
This is only relevant for L2 afaik.

Trace formatted identically to trace.txt in example.

Then additional cycles are required to transfer the entire block to L1 (one 32-bit word at a time).

Let PC be the value of the program counter at the address.
Let ABS be the absolute target address.
The immediate value is (ABS-(PC+4))/4
(forward jumps are positive, backward jumps are negative)

Let's hope that there are no test programs that check this.

Something to do with TR1 regex?

Particularly, if a cache is still loading the rest of a block (due to early restart) we should print the cache contents only after it's done loading.
However the time that this takes should not be counted towards execution time or any other statistics.

Uses a limited capacity queue.
Knows when it is throttled by the instruction memory system.

ALU instruction which hits in L1 instruction cache will take l1_access_delay total, for both the cache and the execution.

For the instruction unit