The multi layer template for JLCPCB uses 0.254mm track width while JLC's reference seems to claim 0.09mm minimum track width on the outer signal layers and 0.127 for inner layers (1oz copper).

Unless I'm missing something that seems rather conservative. Was that so it would work for 2oz boards as well? At the same time, the template uses 0.127mm track clearance which I don't think would work with 2oz.

I'm using KiCad 5.1.5 as it comes with Ubuntu 20.04 LTS.
I've copied the AISLER-2Layer and AISLER-4Layer templates to ~/kicad/template.
The File -> New -> Project from Template dialog shows in the tab User Templates two templates. both named AISLER.

It turns out that the value of title from meta/info.html is used, which is for both templates

  <title>AISLER</title>

I've changed them to AISLER-2L and AISLER-4L, now I get unambiguous entries in the selection box.
Minor and trivial change, but I think that the title strings should be unique across all offered templates.

these two things in the title sound wrong to me...

looking at https://jlcpcb.com/capabilities/Capabilities even 1-6 layers seem to use all the same rules.

When using the JLCPCB_1-2Layer template with KiCad 6 the following settings seem to be incorrect:

Copper:
Minimum clearance: 0 mm
Copper to edge clearrance: 0 mm

Silkscreen:
Minimum item clearance: 0 mm

And in Net Classes µVia is larger than Via.

And as said before, there are 4 copper layers active.

Recommended edge clearance 15 mil, with possible removal of copper within 10 mil of the board edge.

An exception is Flex, which actually has a different spec: This has a recommended of 15 mil, but always has removal of copper within 6 mil of the board edge.

I'm not sure how to best represent this in a template (I'll let you decide that), but the values are detailed on our services pages along with our other specs.

Originally posted by @tekdemo in #2 (comment)