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Litex python coding issue
@enjoy-digital
This is a question for Florent.
cf. line 160 of axi_converter.py file.
#SEBO: How to retrieve from LiteX the clock, reset and interface names?
Add extra files (driver, xdc constraints)
Add custom bus interfaces
Add custom bus interfaces
Add version / revision of the IP
Add version / revision of the IP
Add generic management
so far, the HDL code generation does not support the generic parameters.
So, this issue cannot be implemented yet.
Add xci management
Implement IP using xci ips from Xilinx.
Add device list compatibility
Add device list compatibility
Add logo on IP packaging.
Add logo on IP packaging.
XDC generated file
@enjoy-digital Florent,
For a custom IP, the xdc constraint file should focus on timing constraints (clock, false & multicycle paths, ...) and should not include LOC constraints.
Add a AXI Lite interface
Add a AXI Lite interface in the code and package it.
Add Vendor display name & vendor url
Add Vendor display name & vendor url
Add an interrupt interface
Add an interrupt interface in the code and package it.
Add IP documentation
Add IP documentation
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