Comments (3)
@danpage - The load and store instructions are really tight on the encoding space. We can't fit two extra instructions like this which have the same flexibility as their "u" counterparts.
The idea behind the "u" versions was to be able to load a word worth of bytes from different places without needing to do things like shifting and masking.
Given this intended use case, would it be sensible to make the versions of xc.ld.[h|b]u
where the byte/halfword of the destination register is the zeroth one blank the rest of the register. This is a change of functionality to the existing instructions, rather than adding new encodings.
It would mean you can't load to the zeroth byte/halfword of a register without blanking the rest, but I don't see that being much of a constraint if you were going to load the rest of the register with data anyway.
from xcrypto.
xc.ld.b x, y(z)
would then be a pseudonym for xc.ld.bu 0,0,x, y(z)
from xcrypto.
Decision:
- No new dedicated encoding.
- Existing
xc.ld.[b|h]u
whereh
orb
are non-zero continue to behave as before, updating the addressed byte or halfword and leaving the others un-modified. - Existing
xc.ld.[b|h]u
whereh
andb
are both zero will write the loaded bytes to the least significant portion of the destination register. The other high bytes are then cleared. - This means we can still load a complete word-worth of register with disparate memory values without having to do expensive shifts and masks, so long as we always load the least significant byte/halfword first.
from xcrypto.
Related Issues (20)
- xc.gather.b instruction operands HOT 1
- xc.gather.b has wrong bytes when gather bytes at some offset possitions.
- RWC Publicised Release Checklist HOT 1
- Instruction Modification: xc.msll.i, xc.msrl.i shift amount HOT 1
- Spec typo: xc.mix.* instruction registers
- xc.ext and xc.ins syntax in specification
- xc.prot specified with cshamt field rather than crs2 HOT 1
- Instruction Proposal: xc.bop.3 HOT 1
- Benchmarking: aes-test example HOT 1
- Encoding fixes needed for multi-precision instructions HOT 1
- XCrypto Repository management todo list. HOT 2
- Re-encode the multi-destination register instructions.
- Pack width use cases
- Packed shift by immediate - shamt field should be narrower
- Change operand ordering of xc.mror
- Instruction Change: xc.aessub enc rot HOT 1
- Equivilent RISC-V instruction listing HOT 1
- Review Bitmanip borrowings
- Re-instate the FENL instructions on v1.1.0 branch
- [Masking ISE] - Broken checkout of spike.
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from xcrypto.