The code repository of DGCNN on FPGA: Acceleration of The Point Cloud Classifier Using FPGAs
License: GNU General Public License v3.0
Dear author, hello.
I encountered an error while doing the make compile_swemu step.
The error message is as follows:
ERROR: [XOCC 60-602] Source file does not exist: /home/ic/work/DeepPoint-V2-FPGA/build/4
ERROR: [XOCC 60-623] Unsupported input file type specified.
Every module reports this error.Do you have any idea how to solve this problem?
Wish you a happy life!
Thw Project is nice! I have one question:
In DGCNN, there are many reshape operations used in edge_feature, but I didn't see any related kernel implementation. How is this handled?
hello,I try to use U200 to test the code, where should I modify
Hello, when I execute make compile_swemu，the following error occurs：
===>The following messages were generated while performing high-level synthesis for kernel: task_topk Log file: /home/zyt/Project/DeepPoint-V2-FPGA/bui ld/_x/task_topk_solution/task_topk/vitis_hls.log :
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/ kernels/topk_mergesortdf_pe.cpp:551:29
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/ kernels/topk_mergesortdf_pe.cpp:555:29
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/ kernels/topk_mergesortdf_pe.cpp:559:29
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/ kernels/topk_mergesortdf_pe.cpp:563:29
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/ kernels/topk_mergesortdf_pe.cpp:567:29
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/ kernels/topk_mergesortdf_pe.cpp:571:29
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/ kernels/topk_mergesortdf_pe.cpp:575:29
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/ kernels/topk_mergesortdf_pe.cpp:579:29
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/ kernels/topk_mergesortdf_pe.cpp:583:29
ERROR: [v++ 207-3772] use of undeclared identifier 'streamReadToW1'; did you mean 'streamRead_W1'?: /home/zyt/Project/DeepPoint-V2-FPGA/src/fpga/xilinx/ kernels/topk_mergesortdf_pe.cpp:587:29
The code specified in the error log that I checked is as follows: code
#pragma HLS DATAFLOW
Stream<PairDataIndex_t, 8> streamRead_W1[UnitCount][2];
//#pragma HLS RESOURCE variable=streamRead_W1 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamRead_W1 depth=8
Stream<PairDataIndex_t, 2> streamW1_W2[UnitCount][2];
//#pragma HLS RESOURCE variable=streamW1_W2 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=2
Stream<PairDataIndex_t, 4> streamW2_W4[UnitCount][2];
//#pragma HLS RESOURCE variable=streamW2_W4 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=4
Stream<PairDataIndex_t, 8> streamW4_W8[UnitCount][2];
//#pragma HLS RESOURCE variable=streamW4_W8 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=8
Stream<PairDataIndex_t, 16> streamW8_W16[UnitCount][2];
//#pragma HLS RESOURCE variable=streamW8_W16 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=16
Stream<PairDataIndex_t, 32> streamW16_W32[UnitCount][2];
//#pragma HLS RESOURCE variable=streamW16_W32 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=32
Stream<PairDataIndex_t, 64> streamW32_W64[UnitCount][2];
//#pragma HLS RESOURCE variable=streamW32_W64 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=64
Stream<PairDataIndex_t, 128> streamW64_W128[UnitCount][2];
//#pragma HLS RESOURCE variable=streamW64_W128 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=128
Stream<PairDataIndex_t, 256> streamW128_W256[UnitCount][2];
//#pragma HLS RESOURCE variable=streamW128_W256 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=256
Stream<PairDataIndex_t, 512> streamW256_W512[UnitCount][2];
//#pragma HLS RESOURCE variable=streamW256_W512 core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=512
Stream<PairDataIndex_t, 20> streamW512_Write[UnitCount];
//#pragma HLS RESOURCE variable=streamW512_Write core=FIFO_LUTRAM
#pragma HLS STREAM variable=streamReadToW1 depth=20
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