Buffer sync to frame_clock.

Samples including control bits are currently inside do_samples. Only VHDL 2008 supports specifying std logic vector size inside vectors. VHDL 2008 is not fully supported by Quartus and the project must be compiled and synthesized by Quartus. Thus it's necessary to split samples into the sample itself and control bits, ie. do_samples, do_control_bits.

• Clock generator generating multiframe clk from device clk
• Support for phase adjusting clocks, mainly the multiframe clk, frame clk should be based off of that
• Support for SYSREF, phase adjusting multiframe clk when SYSREF ticks
• Support for enabling SYSREF phase adjustment only before synchronziation
• Support for phase adjusting multiframe clock to x ticks after SYSREF.
• Deassign sync only on multiframe clock
• Adjust buffer size of lane_alignment according to rules set
• Implement specific RBD (buffer delay)
• Make RBD configurable for multipoint link

Support should be implemented to work with multipoint links.

Not all integers have range specified, that could lead to bigger design after synthesis unnecessarily.

Accept ci_realign. If true, realignment will be performed immediately, not at next /A/ as currently.

To jesd204b_rx?

Currently the data link assumes full synchronziation after 4 /K/ characters. That's not correct according to the JESD204B standard. 4 more correct 8b10b characters must be received to assume full synchronization. Until full synchronization is achieved, any error triggers reinitialization.

Currently data link layer input is one 10-bit character. It could be useful to accept N characters at once. That would decrease the frequency needed. The implementation of that should not be that hard. The only differences are:

• ILAS_parser will need to check all N characters instead of just one
• 8b10b decoder will decode 4 characters at once. Use multiple 8b10b decoder blocks for that.
• lane_alignment will save multiple characters to the buffer, it will detect /R/ in any one of them.
• frame_alignment will save multiple character to the buffer

I think that implementing generic N could be done, but making it a specific number such as 4 will be easier, probably.

Accepting settings (when to resync, whether to realign lane, frame)...

Data link layer must support receiving an indication of error to request synchronization.

The current error handling component must be changed to work with multiframes instead of frames. That is mainly because frames may be too small. Maybe allow setting an arbitrary number of octets to check

To jesd204b_rx entity?

Should enclose multiple jesd204b_link_rx and have individual configuration for each.