Comments (2)
JanLJL
commented on June 19, 2024
This is not part of the current scope of work and, therefore, won't be part of OSACA anytime soon, sorry!
You can check out LLVM-MCA with its -timeline option though if you weren't aware of that yet.
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cod3monk
commented on June 19, 2024
@ychen306 The challenge is to find how the pipeline stages are exactly defined and which data requirements are associated with wich stage. We know of no source, which goes beyond guessing, that could provide us with such information. It is also not clear if this can be measured reliably.
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Related Issues (20)
- Benchmark with xor fails on HSW HOT 1
- Benchmark with test fails on SNB HOT 2
- osaca not terminating HOT 2
- unsupported jmpq instruction in parser_x86att.py
- Hex immediate are not recognized. HOT 7
- Bug with working with A64FX assembly code. HOT 5
- Import asmbench result HOT 1
- Instruction is missing HOT 1
- x86 OR instruction breaks LCD analysis HOT 1
- x86 NOT instruction doesn't add a cycle to the critical path HOT 1
- [ARM] Multiply-accumulate output register dependency not recognized HOT 1
- iacaMarks.h compatibility HOT 1
- [ARM] Incorrect parsing of NEON instructions targeting individual lanes HOT 4
- [ARM] Incorrect dependency graph for store dependent on post-indexed load HOT 1
- Parallel LCD computation fails on macOS HOT 1
- OSACA fails on godbolt.org with KeyError: "Port 'D' not in port list." HOT 1
- Profile OSACA to find out what parts are slow and where we have to change code for performance improvements HOT 2
- Add new u-arch: AMD Zen4 (Genoa)
- Add new u-arch: Intel Sapphire Rapids (SPR)
- Add new u-arch: Neoverse N1 (Ampere Altra Max) HOT 1
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