[ARM] Incorrect parsing of NEON instructions targeting individual lanes about osaca HOT 4 CLOSED

After going through OSACA's parsing code, I noticed that it does parse lane selectors, but expects them in a different format (I'm feeding the parser from the output of objdump in macOS), i.e. something like mov x21, v23.d[0]. I've solved this for now in my code using a regex to rewrite the syntax of the affected instructions.

from osaca.

Hi @dgazzoni,

this is indeed something done in the parser, but I am currently hesitating to implement a fix for this because I cannot reproduce the behavior (unfortunately, I don't have a Mac available).
If I try to compile code with your instruction form, all compilers I can use throw an error stating an unknown mnemonic and unexpected characters following instruction at operand 2.
Can you provide me with more information about the compiler and OS you used? Also, which flags are you using for objdump?

Thanks!

from osaca.

This appears to be a quirk of Apple's syntax for aarch64 assembly, and probably not the only one. Here's the requested info:

% sw_vers
ProductName:		macOS
ProductVersion:		13.2
BuildVersion:		22D49

% clang --version
Apple clang version 14.0.0 (clang-1400.0.29.202)
Target: arm64-apple-darwin22.3.0
Thread model: posix
InstalledDir: /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin

% objdump --version
Apple LLVM version 14.0.0 (clang-1400.0.29.202)
  Optimized build.
  Default target: arm64-apple-darwin22.3.0
  Host CPU: apple-a12

  Registered Targets:
    aarch64    - AArch64 (little endian)
    aarch64_32 - AArch64 (little endian ILP32)
    aarch64_be - AArch64 (big endian)
    arm        - ARM
    arm64      - ARM64 (little endian)
    arm64_32   - ARM64 (little endian ILP32)
    armeb      - ARM (big endian)
    thumb      - Thumb
    thumbeb    - Thumb (big endian)
    x86        - 32-bit X86: Pentium-Pro and above
    x86-64     - 64-bit X86: EM64T and AMD64

% echo "mov.d x21, v23[0]\numov x21, v23.d[0]" > test.S

% clang -c test.S

% objdump -d test.o

test.o:	file format mach-o arm64

Disassembly of section __TEXT,__text:

0000000000000000 <ltmp0>:
       0: f5 3e 08 4e  	mov.d	x21, v23[0]
       4: f5 3e 08 4e  	mov.d	x21, v23[0]

from osaca.

Ok, with clang I could verify the correctness as well, thank you!

I now implemented the parser to take indexed registers without a shape/lanes and applied the database lookup in a similar way to the GAS suffixes. Whenever there is a mnemonic with a ".", i.e., this also includes condition codes such as eq, ne, etc... , OSACA checks first for the specific instruction and - if nothing is found - then for the instruction excluding the suffix, i.e., b.ne falls back to b, mov.d and mov.s fall back to mov if not specified explicitly in the DB.
All of this is included from commit 9f715c0 onwards.

If this isn't sufficient in your eyes, please let me know, reopen the issue and we can discuss other alternatives!

from osaca.