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XiaoYu Hong's Projects

ridecore icon ridecore

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

rtl-automata icon rtl-automata

RTL-AUTOMATA is a RTL automatic build script based on shell script and makefile.

ruce icon ruce

Rocaloid UTAU Compatible Engine

rv51 icon rv51

A RISC-V emulator for the 8051 (MCS-51) microcontroller.

sandnix icon sandnix

A Unix-like POSIX-compatible operating system.

scr1 icon scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

serv icon serv

SERV - The SErial RISC-V CPU

shecc icon shecc

A self-hosting and educational C compiler

sky130_rf_tools icon sky130_rf_tools

Guides and templates for using open source RF design tools with the SkyWater SKY130 process.

soc-kc-ls1u icon soc-kc-ls1u

As a salute to the guy who inspired me to become EE engineer. This is the RTL version of his homebrew CPU core (KC-LS1u)

sp-i586 icon sp-i586

soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk contained in the SPI flash.

sv2v icon sv2v

SystemVerilog to Verilog conversion

uc-os3 icon uc-os3

ยตC/OS-III is a preemptive, highly portable, and scalable real-time kernel. Designed for ease of use on a huge number of CPU architectures.

verilogemulator icon verilogemulator

A simple verilog language emulator in electrical engineering writen in c++

vscode-teroshdl icon vscode-teroshdl

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

xboot icon xboot

The extensible bootloader for embedded system with application engine, write once, run everywhere.

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