I will implement a version of fpga-hdl2bit based on edalize, to check similarities and differences. @mithro

Firstly, thanks for doing work to improve Yosys compatibility with existing Xilinx code bases. The work is greatly appreciated! I'm very interested in supporting any work which makes Yosys a more viable synthesis frontend.

You might find the project at https://github.com/SymbiFlow/fpga-tool-perf interesting. The project aims to compare performance of Vivado (and maybe in the future ISE) and the open source tools on important designs. It's more focused on "whole designs" and performance rather than compatibility but could still be interesting to you.

We have recently ported the project t use @olofk's EDAlize project for interacting with the FPGA toolchains.

There are also a simple design doc around this project at https://docs.google.com/document/d/16L50pyS3RjYStvRKRoWyVac7NoZKyu45fpPQXJqeKYo/edit

BTW You might also find the following things interesting;

• Collaboration between Google, Uni of Toronto, Xilinx and SymbioticEDA around FPGA interchange formats which is been worked on at https://interchange.vtr.tools/
• SystemVerilog linter and code formatter - https://github.com/google/verible
• SystemVerilog parser + preprocessor - https://github.com/alainmarcel/Surelog
• SystemVerilog Test Suite - https://symbiflow.github.io/sv-tests/ && https://github.com/SymbiFlow/sv-tests

Hi @rodrigomelo9,

This type of project seems like it would be an excellent addition to the SymbiFlow project. Did you want to join forces here?

The rest of the SymbiFlow project is using the following tools, so it would probably would be good to use them too?
(a) Support using conda to get latest version of tools. Should also make it easier to test multiple versions too.
(b) Use edalize for toolchain interfacing. Use FuseSoC for design integration.

Thoughts?

Tim "@mithro" Ansell

The repo is here. The last commit was in 2017, but it seems that there are a lot of cores which can be used to detect (or not :P) problems with Yosys (because is Verilog 2005).

It seems that you are using, or suggesting to use, docker images that are maintained/released from ghdl/docker, in order to avoid building ghdl and ghdl-yosys-plugin. Precisely image ghdl/synth:beta is used in https://github.com/rodrigomelo9/verifying-foss-hdl-synthesizers/blob/master/helpers/ghdl.sh

I just wanted to let you know that image ghdl/synth:beta does include a fully usable yosys (apart from ghdl-yosys-plugin and ghdl). Hence, you can update the README not to require installing yosys locally. Furthermore, image ghdl/synth:yosys exists (which ghdl/synth:beta is based on). This includes yosys only, without ghdl or the plugin.

Other related images are available with nextpnr, symbiyosys, etc. See: https://github.com/ghdl/docker#-cache-5-jobs--max-4--11-images-weekly. Usage examples are available at antonblanchard/ghdl-yosys-blink, https://github.com/ghdl/ghdl-yosys-plugin/blob/master/examples/docker.mk and https://github.com/eine/vhdl-cfg/blob/master/GHDLSynth.py. However, this issue is not about suggesting you to drop your scripts in favour of any of the existing solution. Instead, I just want to let you know about this resources, so that you can hopefully find insteresting ideas/solutions to apply to your own projects.

Last, but not least, for any visiting reader in this issue, I feel that most of ghdl/synth docker images do not really correspond to ghdl's namespace. @mithro is open to hosting them in Symbiflow, so ghdl/synth:yosys, ghdl/synth:nextpnr*, ghdl/synth:symbiyosys, etc. might be moved to symbiflow/* in the near future (as soon as we have time to decouple them from ghdl/docker). See context in ghdl/ghdl-yosys-plugin#95.

Related with the book, there is a repo with almost 860 cores (VHDL and Verilog) taken from OpenCores. It seems a little tricky to deal with, because each IP is in an individual branch, and it seems to be huge (4.5 GB according to this). Maybe could be a good idea an intermediate repository wich extract only the HDL files?

• https://github.com/laforest/FPGADesignElements

Hi @mithro, I read your document, but I need more info about that point :P I will check how to use Conda, and I need an environment which supports:

• Yosys, GHDL and the ghdl-yosys-plugin, iverilog, verilator.
• Python3 and edalize.
• ISE, Vivado and Quartus.

Recommendation/suggestions? How you solve the support for ISE/Vivado? (which means virtual in your document?). Thanks in advance for links or material that you could provide.