This repository contains Valgrind with support for the RISCV64/Linux platform.

The aim of the project is to enable Valgrind for the RV64GC instruction set on the Linux operating system. Once this support is implemented and has sufficient quality, it is intended for this port to become a part of the upstream Valgrind project and to continue further development there.

For installation, please follow the generic steps how to build Valgrind in the main README file.

In case you are interested in helping with the port then the best option is to analyze remaining failing tests in the Valgrind test suite, or just try the port with your application and report any discovered bugs.

The project was presented at FOSDEM 2022.

Current focus is on functionality and correctness.

The following tables summarize the basic state as of 2023-08-29.

The following ISA base and extensions are currently supported:

Notes:

(1) MULHSU is not recognized.

(2) LR and SC use the VEX "fallback" method which suffers from the ABA problem.

(3) Operations do not check if the input operands are correctly NaN-boxed.

(4) CSRRC, CSRRWI, CSRRSI and CSRRCI are not recognized.

(5) Only registers fflags, frm and fcsr are accepted.

(6) FENCE.I is not recognized.

(7) See https://github.com/T-head-Semi/thead-extension-spec

(8) See https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1

(9) See https://github.com/riscv/riscv-v-spec/releases/tag/v1.0

Test results:

This project is released under the terms of the GPLv2 License.