Recreation of the logarithmic 4-bit current steering DAC from AY-8910/AY-8912/AY-8913. Inspired and informed by silicon reverse engineering of the orginal chip.

This work was done as excercise for Zero To ASIC Analog course and will be part of the open-source silicon for AY-8913 and potentially SN76489 unless I manage BJT DAC for it. Also check open-source silicon effort for Z80 CPU.

• Inspect chip in 3D
• Inspect schematics
• Read the documentation for the project

4-bit to 16 lines decoder on the left side. 16 current steering transistors of the different size form the DAC on the right. Output is in the top right corner.

Yeah, it is just bunch of transistors connected in parallel. The real magic is in the width & length of their gates.

First of all, it turns out that there are so many secondary effects, that the theoretical formula W/L=2 * Id / (uCox * (Vdd-Vth)^2) often presented in books becomes practically useless!

The W/L ratio of the gate is non-linear in regards to desired current. 4/2 != 2/1 != 1/0.25 in terms of current. Thinner the gate (in absolute values), stronger are various secondary effects and more resulting current deviates from the theory.

I could not find SKY130 documentation how to model these effects, but I could find some clues in:

• https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html -- (bit cryptic) tables are very illustrative about non-linear effect of W/L on Vth.
• sky130A/libs.tech/combined/continuous/models_fet.spice -- Vth0 depends on W/L in some weird ways, perhaps Cox as well.

See how Vth (threshold voltage) depends on W/L, ranging from 0.434V to 0.64V.

Check out what they have in models_fet.spice though, even weirder:

From my experiments it is very likely that W/L affects not only Vth, but Cox as well.

The behaviors above are actually called Short chanel effects and Reverlse short-channel effect!

I started using gates that are much larger (fatter and longer) than the theory would give me. Making gates larger significantly reduced the secondary effects!

I picked, partially through calculation, partially through experimentation, the sizes for my maxmimum (2mA) and minimum currents (16uA). Which turned out to be really nice numbers 12/1 and 1/12 😎 and used super simple Python script to fit exponential curve through them: for i in range(8): print(12*(0.707**i)

I thought I would have to wiggle the gate sizes in the middle, but it just worked out as is.

If I had my transistors even slightly smaller, it would not be that easy! Right now they are approximately x3 larger than theoretically necessary.

1. Now I see that the 3 "middle" transistors don't exactly follow the pattern and perhaps original designers had to wiggle their W/L ratio.
2. Even the smallest current steering DAC gate is significantly larger than the logic gates next to them (see the image below), even if they control relatively tiny currents. I assume the original designers might have done the same - just make all DAC transistors larger to make it easier to "fit" in the exponential curve without significant distortions.
3. It also could explain why couple of "steps" are bit off from the spec in the original chip.

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