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This project will compile verilog (a hardware description language) into factorio blueprints.

Home Page: https://redcrafter.github.io/verilog2factorio/

License: GNU General Public License v3.0

TypeScript 96.09% Shell 0.03% HTML 1.40% JavaScript 2.48%

compiler factorio verilog

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verilog2factorio's Issues

Non-Deterministic Outputs

Compiling the same file twice does not necessarily produce the same results. This may make it difficult to reproduce or debug errors.

I assume the culprit is the randomness in the simulator. Maybe using a static seed would help?

Feature Request: Operate on the entire vector of signals in a wire

Right now, it seems like the generated blueprint operates on specific signals on circuit wires (wooden box and the V signal).
This is fine for doing general computations where the signal type doesn't matter, but when managing resources, the following features would be useful:

Vector operations on all signals at once (e.g., multiple every signal by 2)
Operate on individual signals by type in the vector (e.g., multiple copper plates by 2; other signals can either be passed through or dropped)
Specify the type of input or output signal (instead of always using wooden box or V)
Modify the type of signals (e.g., set copper ore equal to copper plates; original signal can be passed through or dropped)

...basically adding support for the "each", "anything", and "everything" signals on the circuit combinators

I'm not sure how to represent the operations in verilog, but for the compiled circuit representation, the fCPU mod might give some inspiration (see the "SIMD instructions" section)

Opaque error and stacktrace when unable to compile

An absolutely wonderful project you have here! I was poking around to see if it could work with one of my Verilog projects (https://github.com/wordandahalf/XDN/), but it fails without an easily diagnosable error:

$ npm start ./XDN/rtl/XDN.v 

> @ start /home/ryan/Documents/Workspace/Factorio/verilog2factorio
> node --no-warnings --loader ts-node/esm ./src/main.ts "./XDN/rtl/XDN.v"

Generating netlist
Error: ENOENT: no such file or directory, open './temp.json'
    at Object.openSync (fs.js:476:3)
    at Module.readFileSync (fs.js:377:35)
    at ChildProcess.<anonymous> (file:///home/ryan/Documents/Workspace/Factorio/verilog2factorio/src/main.ts:16:40)
    at ChildProcess.emit (events.js:315:20)
    at ChildProcess.EventEmitter.emit (domain.js:467:12)
    at Process.ChildProcess._handle.onexit (internal/child_process.js:277:12)
npm ERR! code ELIFECYCLE
npm ERR! errno 1
npm ERR! @ start: `node --no-warnings --loader ts-node/esm ./src/main.ts "./XDN/rtl/XDN.v"`
npm ERR! Exit status 1
npm ERR! 
npm ERR! Failed at the @ start script.
npm ERR! This is probably not a problem with npm. There is likely additional logging output above.

npm ERR! A complete log of this run can be found in:
npm ERR!     /home/ryan/.npm/_logs/2021-04-26T20_35_53_644Z-debug.log

$ cat /home/ryan/.npm/_logs/2021-04-26T20_35_53_644Z-debug.log 
0 info it worked if it ends with ok
1 verbose cli [ '/usr/bin/node', '/usr/bin/npm', 'start', './XDN/rtl/XDN.v' ]
2 info using [email protected]
3 info using [email protected]
4 verbose run-script [ 'prestart', 'start', 'poststart' ]
5 info lifecycle @~prestart: @
6 info lifecycle @~start: @
7 verbose lifecycle @~start: unsafe-perm in lifecycle true
8 verbose lifecycle @~start: PATH: /usr/lib64/node_modules/npm/node_modules/npm-lifecycle/node-gyp-bin:/home/ryan/Documents/Workspace/Factorio/verilog2factorio/node_modules/.bin:/home/ryan/.sdkman/candidates/java/current/bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/bin:/usr/share/avr/bin:/snap/bin
9 verbose lifecycle @~start: CWD: /home/ryan/Documents/Workspace/Factorio/verilog2factorio
10 silly lifecycle @~start: Args: [
10 silly lifecycle   '-c',
10 silly lifecycle   'node --no-warnings --loader ts-node/esm ./src/main.ts "./XDN/rtl/XDN.v"'
10 silly lifecycle ]
11 silly lifecycle @~start: Returned: code: 1  signal: null
12 info lifecycle @~start: Failed to exec start script
13 verbose stack Error: @ start: `node --no-warnings --loader ts-node/esm ./src/main.ts "./XDN/rtl/XDN.v"`
13 verbose stack Exit status 1
13 verbose stack     at EventEmitter.<anonymous> (/usr/lib64/node_modules/npm/node_modules/npm-lifecycle/index.js:332:16)
13 verbose stack     at EventEmitter.emit (events.js:315:20)
13 verbose stack     at ChildProcess.<anonymous> (/usr/lib64/node_modules/npm/node_modules/npm-lifecycle/lib/spawn.js:55:14)
13 verbose stack     at ChildProcess.emit (events.js:315:20)
13 verbose stack     at maybeClose (internal/child_process.js:1048:16)
13 verbose stack     at Process.ChildProcess._handle.onexit (internal/child_process.js:288:5)
14 verbose pkgid @
15 verbose cwd /home/ryan/Documents/Workspace/Factorio/verilog2factorio
16 verbose Linux 5.11.12-177.current
17 verbose argv "/usr/bin/node" "/usr/bin/npm" "start" "./XDN/rtl/XDN.v"
18 verbose node v14.16.1
19 verbose npm  v6.14.12
20 error code ELIFECYCLE
21 error errno 1
22 error @ start: `node --no-warnings --loader ts-node/esm ./src/main.ts "./XDN/rtl/XDN.v"`
22 error Exit status 1
23 error Failed at the @ start script.
23 error This is probably not a problem with npm. There is likely additional logging output above.
24 verbose exit [ 1, true ]

Without diving too much into the code, I have a feeling that yosys fails to synthesize the XDN code and its errors aren't forwarded to stderr/stdout.

Attempts to Construct Overlong Wires

In some cases the compiler might try to construct overlong wires.

I have two guesses for why this might be happening:

This only happens for constant combinators. Since they don't line up with the normal "grid" of 2x1 combinators, the assumptions about distance can be wrong.
This only happens for input/output nodes. I don't think this is very likely from what I have seen of the code.

Image of an affected blueprint (with some combinators removed for clarity).

I've double-checked that these wires can't be constructed in-game.

Blueprint:
https://gist.github.com/birdbrainswagtrain/b719b2c88bda39aa7a40ba6e5ceb9333

Compiled blueprint does not have expected behavior

I've tried several variations on this code, but never gotten compiled combinators with the expected behavior.

module priority(input clock, input [9:0] prevPriority, input [9:0] f, input complete, output [9:0] priority);
    always @(posedge clock) begin
        if (complete)
            priority <= prevPriority;
        else if (prevPriority > f)
            priority <= prevPriority;
        else
            priority <= f;
    end
endmodule

If the complete input is set, this is supposed to output prevPriority. If the complete input is clear, this is supposed to output either f or prevPriority, whichever is larger.

The observed behavior is that copying f to priority works fine, but whenever it is supposed to output prevPriority, it outputs 0 instead.

The blueprint from v2f is

0eNrtmN1umzAUx9/F16SKDYSAtN3sASbtojdVhAictJbARsZEiyLefTY0WUIDsVm2tspuKtnYx8f/3/lwukfrvIZSUCZRtEdUQoGikzkH5ckacjWnxlxQuVNTNOWsQtHTHlX0mSW53il3JahVrQEHsaTQowxSmoGYpbxYU5ZILlCjtrMMfqIIN85VA/ogmTB52QJpVg4CJqmk0PnTDnYxq4s1CHXEqCEHlbxSeznT5yt74YPvoB2KZvjBV6dkVEDaffYcbUEKnsdreEm2Sgq9Z0NzCWJAii0VslYzRx+6FbNHfYOU11rx+Ykaq3aase7MSlvC+o+A7PRuVI2w2pdSkdZUdmMtxLMAUK4+rZpGK9uTgthJgeefRYvAWgrXUgr8WaRYWEvhWUpBPrAUJ5c9UyV8o8pFKfyjFwVktC5mkKtzBE1nJc/hghbuuRamqYvP3SEnrrTfiTXExdHzRBXolwKkctoool0jhr+txupzRo933FBRydgOawXaRnwItxYwL0EknQvo+w+1j9eyrC0sf0NaGFMEbl/hHgFvlICDyM0qUTDWKYdrshm2V5O3Y2aDQ7tUlIlobxKhr0hPlLu4zep4I3gRU6YYo2iT5BXYI3+0Qr4YTzpyJSL8iRGxtI6IpXUuH4IC32UuB32whmRCazLh5Cr7fmTsMvaP0dnl5HIE3dnCt/V4BCx2rcnq17QlWnLXSYfNy+EQU4zNXmUY27VI99+3yNdud8CBe63vy3Drk6L+652v37vIldfOcBr2f3QavFxH8nSspY6aJUORQqZFCn63SJl/sEgh43zNiWGrgk2m2h2MBHdyq/bvsp6H5o+oQTaeYT337LKUWIG5gyxdGGeLe6Vc+1ZZio3P9Q2z1J8WCf87u8G/G67m5k1Ie5dIq9VbEFULhyyxF4QkcD0v8IjXNL8AqM1S6Q==

Here I have connected it to a 1/2 second clock, and set prevPriority to 400 and f to 350. The expected output in this case is 400, but the observed output is 0. I also tried 60 Hz (always-set) and 30 Hz clocks, with the same result.

0eNrtWcuOmzAU/RevyYiXDUFtN/MBlbqYTRUhAs6MJTDImKhRxL/XJp0kQ3jYkCZRp5soPHx9fc65D5s9WKcVLhihHAR7QOKcliD4uQcleaVRKu/xXYFBAAjHGTAAjTJ5leCYJJgt4jxbExrxnIHaAIQm+BcIrNoYNRAxwt8yzEncbcOuVwbAlBNO8MGj5mIX0ipbYyYmGfLFAEVeiqE5lQ4IcwvkLZ+gAXbir4OQmCchDMeHN1wDiHVzlqfhGr9FWyIsiGF/7IbiWdLYKuXdDWElDy9WtyWMV+LO0avDG4sXuSaJKo8kxI4pr7IiYo2fAfgiRuQVLyp9m8VOuFZRHm5YnoWEChsg4KzC9WFKelhf47UlfxhOzpEkSYNiTFhcEd5c2pK5s8eCBWHLVhtstQY77ceruj575Z1I+7i8d5g0mPSeoBKXG5JyzHqkPYJzJYmzztS9moxvHwbODDG7dxOz1dLy1ytreROl5SwxD4kX9lDhasvRP3Fh30qOrmlOFKRiVMI5UXkzGCaC4AxnPctUwwhpY+TdASMHTpWKqwaDpw0DelCpvDKM6QUMijncP86e4YRU2QKnwj4TDU6Rp7gTB9jGQZUZe7jyWugyE3a5vBxpx0aynanE3Mn0FYpPiaWN8FSDBK15gUUFalwA339MqEHPoK6nZ9CRHklRPTLnaHOBPjsX8IR9d+wiRfStCeh7j4C+DrBXoOdFi57lRaQY3Tx5wzHkK7Jo67bRUJfCq7TRzx/baPMvt9GaW0K/XUxsVRa7om2A1Ysipmq3r5xZ2tuoUzGD/o23UZPi94NOvt15u+W2heKOtNVQRx5LxZh3Z2VuRdr/tbqJ2tR4WpGruIe0oG48oo/E3CoDW4+VgTvw7cuMeryhqXZ7My6aXnFvmXEfnG84kjg95QpsjliydfTi989jK+rDm5EB0P+OrPcgpo8XOHIw4GvtXdHUeXv14M+r1uhznjj0H2wrV4Vactd8ggvOPvkZYItZ2SzE9i3XW9qe47smcs26/g3V+I5r

I suspect the issue is one of the C = 1 deciders; it has an input of C=351. I have reversed that decider (so it points up, instead of down) in the second blueprint. It is also very possible that I'm showing my lack of experience with verilog, but in that case, I don't know where to start debugging.

v2p is 97317fd0ec7358791967bb1b7a002746cad1abfb, and yosys was built from d8c5d6815cc80af852ce0969e4cf775f44539c80. Node is v14.17.0.

redcrafter / verilog2factorio Goto Github PK

verilog2factorio's People

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verilog2factorio's Issues

Non-Deterministic Outputs

Feature Request: Operate on the entire vector of signals in a wire

Opaque error and stacktrace when unable to compile

Attempts to Construct Overlong Wires

Compiled blueprint does not have expected behavior

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