Comments (5)
This happens when you have two instances of objects with the same name, then Veriloggen treats them as two different modules as they have the same name. It adds an underscore to differentiate in Verilog.
m = Module("top")
param = []
port = []
counter = Module("counter")
m.Instance(counter,"i0",param,port)
m.Instance(counter,"i1",param,port)
print(m.to_verilog())
module top
(
);
counter
i0
(
);
counter
i1
(
);
endmodule
module counter
(
);
endmodule
from veriloggen.
This happens when you have two instances of objects with the same name, then Veriloggen treats them as two different modules as they have the same name. It adds an underscore to differentiate in Verilog.
m = Module("top") param = [] port = [] counter = Module("counter") m.Instance(counter,"i0",param,port) m.Instance(counter,"i1",param,port) print(m.to_verilog())
module top (
);
counter i0 ( );
counter i1 ( );
endmodule
module counter (
);
endmodule
It works!!! I temp to use str type Stubmodule and cause a "_".
Thank you!!!
from veriloggen.
Multiple creation of module with the same module name causing a "_" appended at the end.
from veriloggen.
I'm now considering to disable this behavior that appends _
to the module name.
from veriloggen.
This issue has been resolved in 06b3490 .
from veriloggen.
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from veriloggen.