Comments (2)
Hi,
You need to pass the parameter True on the assignment to get the blocking assignment.
myvar= m.Reg ('myvar', width = 4 , initval = 0 )
logic_wire= m.Reg ('logic_wire', width = 1 , initval = 0 )
decCond = []
decCond.append (vg.When ( 0 ) (logic_wire ( 1 ,True)))
# ... more conditions ...
decCond.append (vg.When () (logic_wire ( 5 ,True)))
m.Always( ) ( vg.Case (myvar) (* decCond ) )
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Cool, obrigado Lucas, it does work indeed
It would be awesome to throw all these examples into the wiki, it should not take long and save you guys a bunch of qeustions!
from veriloggen.
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