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Since EV3a algorithm has already existed. As a result, we would like toimprove it performance by realizing a specific hardware architecture.Common technique in digital design involve pipelining, caching and so on.In this final project, we’ll be using these technique to reduce timecomplexity of EV3a algorithm.
- prime time power
- dc power(saif file)
[1] Benjamin Doerr, Frank Neumann. Theory of Evolutionary Computation. Springer Cham.2020.
[2] G. Andrey and N. Thirer, "A FPGA implementation of hardware based accelerator for a generic algorithm," 2010 IEEE 26-th Convention of Electricaland Electronics Engineers in Israel, 2010, pp. 000578-000580,doi: 10. 1109/EEEI.2010.5662152
[3] MIT 6.375 complex digital system. Arvind,
>> http://csg.csail.mit.edu/6.375/6_375_2019_www/index.html
[4] Heather Berlin, Zachary Zumbo. Hardware Accelerated Genetic Optimization for PCB Layer Assignment .
>> http://csg.csail.mit.edu/6.375/6_375_2019_www/handouts/finals/Group_1_report.pdf
[5] ECE 4514 Digital Design II Spring 2008 Lecture 6: A Random Number Generator. Patrick Schaumont.
>> https://schaumont.dyn.wpi.edu/schaum/teaching/4514s19/
We would like to ackowledge Professor Lindor for his mentorship and guidance throughout the research, design and implementation of this project. Without him, there would be no final implementation of this project, so as my EC Teammate. You can fellow their github. Here is the superconnection of their github. Thanks~
sicajc : https://github.com/sicajc
Alchemist-Kang : https://github.com/Alchemist-Kang