pthalin / video_lag_tester Goto Github PK

Hello :)

I just received everything I need to make my own video_lag_tester :)

Are you thinking about using making the code FOSS ?

Unable to see the resolution most of the time in the top right corner as it’s cut off and into the overscan area

When trying to program my Tang Nano 4K on my Windows 11 PC I was getting the error above. After some digging, I found the solution which requires a few steps.

Install Zadig. Go into options and list all devices. Select JTAG Debugger (interface 0). In the driver field right of the arrow click the arrows until WInUSB is shown. Then click install driver. After that, you'll be able to program the Tang Nano 4K.

Hello @pthalin !

What a cool project ! I just ordered everything need to create my own video_lag_tester.

I wondered if you though about adding an other feature on the video_lag_tester: having the possibility to measure the complete latency of a console by having a gpio that is triggered while pushing on a controller button, and then waiting for a white screen on the display.

The hdmi would be used only to display the measure.

The detailled process for a super nintendo:

• add a pulled up gpio on the L1 positive connector on the controller (3.3v)
• use the 240P test suite, and go on the black screen of RGB and white screen menu
• press L1 to change screen color from black to white
• the calculated lag between the state change on gpio and the white screen will be the complete latency of the system (input lag + process latency + video lag).

We could even make it automatic by controlling the gpio state.

Thanks again for the share of this project !

Dear pthalin, thank you very much for your work on using time-sleuth on Sipeed Tang Nano 4k. For "Display Lag Tester v2", I see that the available versions are 480i60, 480p60, 720p60, 1080i60. Do you plan to make it also for 1080p60? or Tang Nano 4k is not compatible for 1080p60?

Hi there,

I recently got one of the above toys.. adding the project to the Gowin FPGA Designer 1.9.8.10 and changing the target, there are many errors abound. (Complains about Verilig versions and syntax) and in the end it doesnt syntheise.

ERROR (PA2024) : The number(335) of ports exceeds the resource limit 59 regular I/Os and 1 RECONFIG_N I/Os of current device, you can also use 4 JTAG, 3 SSPI and 4 MSPI I/Os by configuring Dual-Purpose Pin as regular I/Os.

its clearly on some or other whacky trip :D Loading the project and not changing anything results in errors..

Any pointers would be appriciated..