To design a half subtractor and full subtractor circuit and verify its truth table in Quartus using Verilog programming.
Subtractor circuits take two binary numbers as input and subtract one binary number input from the other binary number input. Similar to adders, it gives out two outputs, difference and borrow (carry-in the case of Adder). There are two types of subtractors.
The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow). To perform x - y, we have to check the relative magnitudes of x and y. If x ;;, y, we have three possibilities: 0 - 0 = 0, 1 - 0 = 1, and 1 - I = 0. The result is called the difference bit. If x < y, we have 0 - I, and it is necessary to borrow a 1 from the next higher stage. The I borrowed from the next higher stage adds 2 to the minuend bit, just as in the decimal system a borrow adds 10 to a minuend digit. With the minuend equal to 2, the difference becomes 2 - I = 1. The half-subtractor needs two outputs. One output generates the difference and will be designated by the symbol D. The second output, designated B for borrow, generates the binary signal that informs the next stage that a I has been borrowed.
Sum = X'Y+XY' = X ⊕ Y Carry=X'Y
A full subtractor is a combinational circuit that performs subtraction involving three bits, namely minuend, subtrahend, and borrow-in . It accepts three inputs: minuend, subtrahend and a borrow bit and it produces two outputs: difference and borrow.
Diff = A ⊕ B ⊕ Bin B = A'Bin + A'B + BBin
Connect the supply (+5V) to the circuit.
Switch ON the main switch.
If the output is 1, then the led glows.
Program to design a half subtractor and full subtractor circuit and verify its truth table in quartus using Verilog programming.
Developed by: P Sri Varshan
RegisterNumber: 22008051
Half Subtractor
module exphalfsub(A,B,Diff,Borrow);
input A,B;
output Diff,Borrow;
assign Diff=(A^B);
assign Borrow=(~A&B);
endmodule
Full Subtractor
module fullsub(A,B,C,diff,borrow);
input A,B,C;
output diff,borrow;
assign borrow = (~A&(B^C)|(B&C));
assign diff = (A^B^C);
endmodule
Truth Table for Half Subtractor
Truth Table for Full Subtractor
RTL Realiztion for Half Subtractor
RTL Realization for Full Subtractor
Timing Diagram for Half Subtractor
Timing Diagram for Full Subtractor
Thus the half subtractor and full subtractor circuits are designed and the truth tables is verified using quartus software.