picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

pipecheck

playground-neual-network

Play with neural networks!

pqr5asm

PQR5ASM is a RISC-V Assembler compliant with RV32I

priyanshu.github.io

Personal website

priyanshumishra77

pulp

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

pulpissimo

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

pulp_cluster

The multi-core cluster of a PULP system.

pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

python4rtlverification

pytorch-tutorials

PyTorch tutorials for beginners

pyvsc

Python packages providing a library for Verification Stimulus and Coverage

qemu

Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

reindeer

PulseRain Reindeer - RISCV RV32I[M] Soft CPU

resumegenerator

A tool used to create HTML document Resumes

retraining-free-pruning

[NeurIPS 2022] A Fast Post-Training Pruning Framework for Transformers

rioschip

rioschip_resubmission

ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

risc-v

Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection, Branch Target Buffer using LRU replacement policy, absolute value custom instruction.

risc-v-cpu

A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

risc-v-guide

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

risc-v-processor

DUTH RISC-V Microprocessor

risc-v-processor-design

A verilog based 5-stage pipelined RISC-V Processor code.

risc-v-processor-implementation

Verilog implementation of multi-stage 32-bit RISC-V processor

risc-v-simulator

Assembler and Simulator for RISC-V RV32I instruction set that runs entirely in web browser.

risc-v-superscalar-ooo

DUTH RISC-V Superscalar Microprocessor

risc-v-vector

Vector processor for RISC-V vector ISA

riscv

RISC-V CPU Core (RV32IM)