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Name: Priyanshu Mishra

Type: User

Bio: Design Verification Engineer

Twitter: Priyans57411485

Location: Bangalore

Hi Everyone 👋 I'm VLSI AND COMPUTER ARCHITECTURE & I like Priyanshu

Computer Architecture and Verification Engineer

A passionate VLSI Engineer

🌱 Inspired by UC Berkeley/MIT classes, Teaching CS 250 VLSI, CS 152/252A undergraduate & graduate computer architecture, High-performance RISC-V CPU Design and Verification(Architecture and sub-system level)
🌱 I’m currently learning HPC
👨‍💻 All of my D-I-Y projects will be available soon at https://github.com/Priyanshumishra77
💬 Ask me about Computer Architecture, VLSI and AI-Hardware
📫 How to reach me [email protected]
⚡ Fun fact Not sure

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Priyanshu Mishra's Projects

8-bit-computer

[Computer Engineering] Programmable 8-bit computer based on von Neumann architecture, designed and implemented from scratch in Logisim.

8-bit-cpu

RTL code of an 8-bit CPU designed in Verilog with a separate file for each module.

amos

Automatic Mapping Generation, Verification, and Exploration for ISA-based Spatial Accelerators

annotated_deep_learning_paper_implementations

🧑‍🏫 59 Implementations/tutorials of deep learning papers with side-by-side notes 📝; including transformers (original, xl, switch, feedback, vit, ...), optimizers (adam, adabelief, ...), gans(cyclegan, stylegan2, ...), 🎮 reinforcement learning (ppo, dqn), capsnet, distillation, ... 🧠

apbi2c

APB to I2C

applecpu

Apple Firestorm/Icestorm CPU microarchitecture docs

applegpu

Apple G13 GPU architecture docs and tools

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

ariane

Ariane is a 6-stage RISC-V CPU

awesome-generative-ai

A curated list of modern Generative Artificial Intelligence projects and services

awesome-generative-ai-guide

A one stop repository for generative AI research updates, interview resources, notebooks and much more!

awesome-generative-ml

A curated list of Generative AI tools, works, models, and references

awesome-open-hardware-verification

A List of Free and Open Source Hardware Verification Tools and Frameworks

aws-fpga

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

aws-neuron-sdk

Powering AWS purpose-built machine learning chips. Blazing fast and cost effective, natively integrated into PyTorch and TensorFlow and integrated with your favorite AWS services

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

best-websites-a-programmer-should-visit

:link: Some useful websites for programmers.

biriscv

32-bit Superscalar RISC-V CPU

black-parrot

A Linux-capable RISC-V multicore for and by the world

branch-predictors

Branch predictor project for Computer Architecture course. Implementation of state-of-the-art TAGE predictor is included.

briski

BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput and compute density to increase the amount of cores in many-core design without sacrificing performance.

buddy-mlir

An MLIR-based compiler framework bridges DSLs (domain-specific languages) to DSAs (domain-specific architectures).

build-your-own-x

Master programming by recreating your favorite technologies from scratch.

bullseye

BullsEye: A Scalable cache miss calculator for affine programs

cache-coherency-protocols

Implementation of MI, MSI, MESI, MOSI, MOESI, MOESIF protocols in Cache Coherence

cache-mapping

Storing data in 16-bit multilevel Direct Mapped, Associative, N-way Set Associative cache memory

caltech10-cpu

8-bit Harvard Architecture CPU implemented in ABEL

caravel

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

carfield

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.