priontu / spartan-3-fpga-seven-segment-decoder Goto Github PK

Used VHDL to program the Seven-Segment Display of the Spartan-3 FPGA board so that the leftmost display showed the hexadecimal value of the binary input provided by the leftmost 4 switches, the second leftmost display showed the hex for the input from the last 4 switches, and the next two displays showed the hex value of the sum of the two leftmost displays. Developed a clock divider and segment decoder, and put it together with a top design to execute the display decoder.

License: MIT License