Comments (4)
chelini
commented on August 24, 2024
I believe here the problem to be that your matcher looks for a 2d store but what you really want is to math a 4d store. Try with: m_Op<AffineStore>(m_Any(), m_Any(), m_Any(), m_Any())
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IsolatedMy
commented on August 24, 2024
I believe here the problem to be that your matcher looks for a 2d store but what you really want is to math a 4d store. Try with:
m_Op<AffineStore>(m_Any(), m_Any(), m_Any(), m_Any())
It works. I matched the affine.store op with the following:
matchPattern(store, m_Op<AffineStoreOp>(m_Any(), m_Any(), m_Any(), m_Any(), m_Any(), m_Any()))
Here, since the definingOp of operand of affine.yield is from another affine.parallel op, affine.store can not be located with m_Op so I have to choose to directly capture affine.store op.
In this situation, can I use m_Capture to capture the affine.store op?
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chelini
commented on August 24, 2024
Can you please share the IR you want to match? I am not sure I understood
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IsolatedMy
commented on August 24, 2024
The following is part of MLIR code generated from plaidml/edsl/examples/conv_2d_dilated.cc. What I actually want to match I is the affine.parallel block of %3.
stdx.closure(%arg0: memref<1x244x244x1xi64>, %arg1: memref<3x3x1x32xi64>, %arg2: memref<1x240x238x32xi64>) -> memref<1x240x238x32xi64>{
%2 = affine.parallel (%arg3, %arg4, %arg5, %arg6) = (0, 0, 0, 0) to (1, 240, 238, 32) reduce ("assign") -> (memref<1x240x238x32xi64>) {
%4 = pxa.load %1[%arg3, %arg4, %arg5, %arg6] : memref<1x240x238x32xi64>
%5 = pxa.reduce assign %4, %arg2[%arg3, %arg4, %arg5, %arg6] : memref<1x240x238x32xi64>
affine.yield %5 : memref<1x240x238x32xi64>
}
%3 = affine.parallel (%arg3, %arg4, %arg5, %arg6, %arg7, %arg8, %arg9) = (0, 0, 0, 0, 0, 0, 0) to (1, 240, 238, 32, 3, 3, 1) reduce ("assign") -> (memref<1x240x238x32xi64>) {
%4 = affine.load %arg0[%arg3, %arg4 + %arg7 * 2, %arg5 + %arg8 * 3, %arg9] : memref<1x244x244x1xi64>
%5 = affine.load %arg1[%arg7, %arg8, %arg9, %arg6] : memref<3x3x1x32xi64>
%6 = arith.muli %4, %5 : i64
%7 = affine.load %2[%arg3, %arg4, %arg5, %arg6] : memref<1x240x238x32xi64>
%8 = arith.addi %7, %6 : i64
affine.store %8, %2[%arg3, %arg4, %arg5, %arg6] : memref<1x240x238x32xi64>
affine.yield %2 : memref<1x240x238x32xi64>
}
stdx.yield %3 : memref<1x240x238x32xi64>
}The following code is my capture() function. Now it can match this parallel block and output "Matched". But I don't know how to capture affine.store op and pack it with other affine.load ops into StencilCapture struct.
Optional<StencilCapture> capture() {
using matchers::m_Any;
// Looking for load..load..mul..load..add..store
Value load1, load2, load3, store;
if (!isa<AffineStoreOp>(*std::prev(op.getLoopBody().front().end(), 2))) {
return llvm::None;
}
auto yield = llvm::dyn_cast<mlir::AffineStoreOp>(std::prev(op.getLoopBody().front().end(), 2));
if (matchPattern(yield, m_Op<AffineStoreOp>(
m_Op<arith::AddIOp>(
m_Capture(&load3, m_Op<AffineLoadOp>()),
m_Op<arith::MulIOp>(
m_Capture(&load1, m_Op<AffineLoadOp>()),
m_Capture(&load2, m_Op<AffineLoadOp>())
)
),
m_Any(),
m_Any(),
m_Any(),
m_Any(),
m_Any()))
) {
IVLOG(2, "Matched");
// return StencilCapture{{store}, {load1, load2, load3}};
return llvm::None;
}
return llvm::None;
}from plaidml.
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