Verilog digital circuits/hardware coding lab assignments from 2nd Year of Computer Engineering University

• Using Schematic Designs in Quartus Prime

• Part 1: Quartus Prime Intro Using Verilog Designs, and running simulations on a multiplexer using ModelSim
• Part 2: Verilog implementation of 7400-series chips and 2-to-1 multiplexer
• Part 3: Verilog HEX 7-segment decorder

• Part 1: Designing a 6-to-1 multiplexer using always block and case statements
• Part 2: Building a 4-bit Ripple Carry Adder using Full Adder Circuits
• Part 3: A full ALU that performs functions on to data inputs (A, B)

• Part 1: Gated D Latch implemented using 7400 series IC chips
• Part 2: ALU with 8-Bit Register (edge-triggered Flip Flop) used to store results
• Part 3: 8-Bit Rotating Register with Parallel Data Load

• Part 1: 8-Bit Counter built using T-type Flip Flops
• Part 2: HEX counter that displays digits at different speeds using clock rate divider
• Part 3: Morse Code encoder and display module using LUT, shift register, and clock rate divider

• Part 1: 1 and 0 Sequence Detecting FSM
• Part 2: Quadratic Polynomial Computer: full Datapath and Control Path
• Part 3: 4-Bit Restoring Divider Digital Circuit