In your sample, you use the function add_ip.write() to send data and add_ip.read() to receive data.There is a parameter in the function that i guess it the address of memory.So, i am wondering that where could i find the information of address.Looking forward to your reply!

Hi,

first at all thank you very much for the simple PYNQ overlay examples, they have been very helpful in creating my own overlays.

I based my tcl scripts on you examples and just found a tricky bug that resulted from the following line:

add_files -norecurse [make_wrapper -files [get_files *.bd] -top]

My problem was based on the fact that I added a AXI SmartConnect instance to my block design which in turn generates its own .bd file (e.g. sources_1/bd/system/ip/system_axi_smc_1_0/bd_0/bd_2721.bd). This seems to lead to vivado trying to create a wrapper for the smc instead of the toplevel block design as intended. I fixed this in my project by being more specific about which block design I want to create a wrapper for:

add_files -norecurse [make_wrapper -files [get_files *system.bd] -top]

Since people will be using your scripts as a starting point (as this repo is linked from the official documentation) it might be a good idea to do something similar in the build_all.tcl script. This way the script won't fail if other block designs are added.

Xilinx newbie, but I ran source build_all.tcl and ended up with

Xilinx/Vivado_HLS/2016.1/include/etc/ap_int_sim.h:75:10: fatal error: 'stdio.h' file not found
#include <stdio.h>
         ^
1 error generated.
Failed checking during preprocessing.
    while executing
"source [lindex $::argv 1] "
    ("uplevel" body line 1)
    invoked from within
"uplevel \#0 { source [lindex $::argv 1] } "

child process exited abnormally

Is this just a C HDL thing.

Also in a new overlay build instance once I add the IP I have wrapped my HDL(verilog, ect.) code in to block design can I just throw down a ZYNQ IP block without making any modifications to the ZYNQ IP. And this is assuming that in the vivado project setup I specified the PYNQ-Z1 board files and added the PYNQ-Z1 constraint file.