Name: Macro
Type: User
Company: Qinan
Bio: Microprocessor design and Embedded dev, Linux, open-source hardware/software enthusiast, independent photographer, violin beginner, deep learning beginner.
Twitter: YangMacro
Location: United States, New York
Blog: www.openedf.cn
Macro's Projects
Algorithm Source test.
Must-have verilog systemverilog modules
Deep Learning Examples
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
The Ultra-Low Power RISC-V Core
HDL libraries and projects
kianv a simple implementation of a rv32im riscv cpu and soc in verilog with firmware that runs raytracer, mandelbrot, etc.....
Linux kernel source tree
Linux Device Drivers Development, published by Packt
Linux on LiteX-VexRiscv
Linux driver and unix env programming
This Directory contains the tutorials posted in www.embetronicx.com
The Linux Kernel Module Programming Guide (updated for 5.x kernels)
The root repo for lowRISC project and FPGA demos.
risc-v soft core soc
risc-v core
Software drivers in C for systems without an operating system
RISC-V SoC designed by students in UCAS
Verilog library for ASIC and FPGA designers
Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
OpenXuantie - OpenC910 Core
OpenXuantie - OpenE902 Core
OpenXuantie - OpenE906 Core
Embedded development framework.
PCB Design sources
PicoRV32 - A Size-Optimized RISC-V CPU
practices and test
RISC-V CPU Core (RV32IM)
"Das U-Boot" Source Tree