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I install my test plugin as below:

/ # pb-plugin install /hehlloorld-1.0.pb-plugin

File 'hehlloorld-1.0.pb-plugin' has the following sha256 checksum:

de9d08116cda0163166c55a0cf6a5ba01c7128546df4c7c73967e43547e80596

Do you want to install this plugin? (y/N)
y
3 blocks
Plugin installed
OpenPower Foundation: Hello World Petitboot Plugin Example 1
(version 1.0)

Where can I launch it?

We have found that numerous registers are undocumented, but used in the code (Hostboot). We have also found some cases where the documentation is not consistent with the code (e.g. states the register is read-only, while Hostboot writes there).
Part of the documentation problems (in terms of undocumented registers) we have faced can be found there: https://github.com/3mdeb/openpower-coreboot-docs/blob/main/devnotes/undocumented_registers.md

The docs should be licensed with some sort of Open Source license.

The OPAL is up in the system runtime, here we have software hacks to crash opal, which will trigger S0/S1 interrupts on SBE while going down. Basis those interrupts SBE run the mpipl isteps (which is the same path as Phyp TI)

Mpipl Start Path Istep -

1. istepStartMpipl
2. p9_suspend_powman
3. p9_query_core_access_state
4. istepMpiplRstClrTpmBits
5. p9_sbe_check_quiesce
6. p9_l2_flush
7. p9_l3_flush
8. p9_sbe_sequence_drtm

Mpipl Continue path -

1. istepMpiplSetFunctionalState
2. mpipl_dump_reg
3. mpipl_query_quad_access_state
4. mpipl_hcd_core_stopclocks
5. mpipl_hcd_cache_stopclocks
6. p9_quad_power_off

After this SBE Runs the istep 4& 5 on the Master core, which will trigger the hostbootloader again to start the initial sequence of fetching data from Pnor via Mbox.

Here Mbox fails to réspond like it did in the first boot. May be because it doesn't know the host has gone down and came up again and asking the same questions which he has answered before. (this is as per design to keep bmc agnostic of the host state other than runtime/standby).

Need to see why mbox doesn't respond to initial messages from hostboot loader the second time.

License prevents modification, which is probably not what we want when documenting free software.

Minor issue but, as noted in quoted section below I think it should be POWER9 and not POWER8.

This version of the document will cover all POWER89 systems. Please note that this document has a lot of low level details on the initialization of the POWER processor and it's memory subsystem. There are a lot of terms and details in here that are very IBM and POWER centric. We attempted to put as much in the glossary as possible but please feel free to use the mailing list for any questions.
Throughout the document you will see references to a “SP”. This stands for a service processor and when used it's applicable to either the FSP (Flexible Service Processor – used within IBM POWER based servers) or the BMC (the OpenPower service processor). For the most part we've tried to remove FSP specific references for the OpenPower work but some may still remain for reference in here.
Reading over the Hostboot Programmers guide (same document repo) is reccomended prior to reading this document.
This version of the document will cover the following systems:
IBM FSP based system
Witherspoon – IBM BMC based system
Zaius – BMC based OpenPOWER system

Page 2 of "P9 IPL Flow" document.

Hi, I think i found a mistake in doc(HostBoot_PG.md), it location is
HostBoot_PG.md --> Hostboot Software --> Software Layout --> "There are a variety of other directories under usr/src"
maybe the correct description is "There are a variety of other directories under src/usr". if I am right, please patch and fix it.
ths

We have requirements on what the BMC should initialise and the system configuration that the host assumes for ASPEED BMC-based machines (OpenPOWER).

1. The VUART is used and is present at 0x3f8 in the LPC IO space, using SerIRQ 4
2. The IPMI BT interface is used and is present at 0xe4 in the LPC IO space, using SerIRQ 10
3. The BMC shall perform VGA handover upon detecting the presence of the VGA password in the SCU VGA scratch registers.

Hello,

Is there a way that the document mentioned here could be published:
https://github.com/open-power/hostboot/blob/master/src/usr/intr/intrrp.H#L307

We faced some deadlock during porting coreboot to POWER9. Possibly, we lack some interrupt handling [1].

[1] https://lists.ozlabs.org/pipermail/openpower-firmware/2021-August/000651.html

This IPL flow is an older version, when trying to work issues, I have noticed that isteps have changed from what is in this pdf.