The Zener diode exists in the solder mask / solder paste layers, but is not marked on the silkscreen. I figured out where it's supposed to go based on the board_centroids file, but I'm not sure about its orientation.

At first I thought Zener diodes were bidirectional, but the datasheet is pretty specific that Pin 1 goes over the power line and Pin 2 goes to ground.
See Figure 11: http://www.ti.com/lit/ds/symlink/tpd1e10b06.pdf

Can someone tell me which orientation that should be on the board? See image here:

The Zener diode is in the lower right corner. It looks to me like the ground pin (Pin 2) should be on the left, connected to C1, and the power pin (Pin 1) should be on the right, connected to Polyfuse. But please verify for me. Thanks!

When I connect a I/O board I loose part of the signal (please see the example with test sine) with a presence of a huge offset.
What could be the reason for this?

Hi, I used to run Open-ephys GUI and used it to connect to the acquisition board for biosignal acquisitions. But I met this problem when I recently reinstall GUI in another PC.

I found that during this installation the program called a error:

I'm not sure if the problem of connection might be raised from the C++ library.

On our v2.1 acquisition board with RHD2132 headstages, plugging in a HDMI cable into a digital I/O input port on the board causes an increase in the noise level in the data coming from the headstage (eyeballing it, mostly 60Hz line noise):

HDMI cable unplugged

HDMI cable plugged in

This is with the HDMI cable ground connected to the ground on the acquisition board. (Without this the noise really becomes terrible.) The sine wave is a 77uV 16Hz test signal from our signal generator.

Is this a known issue? Any recommended fixes?

Someone building the board pointed out that a number of components in the Bill of Materials are no longer available from DigiKey. They helped find direct substitutes, which are now listed in the Google Sheet BOM: https://docs.google.com/spreadsheets/d/1ywzGieWArYGw0-nE7zoQLTEWNAr0ZzdUiqCSY4VL7uM/edit#gid=0

Can someone look these over and make sure they look OK? I checked for identical packages and similar specs, but it's always helpful to have another pair of eyes. There are 9 components in total (with a YES in the "UPDATED" column).

Also, there are currently two parallel BOMs, one as a Google Sheet (linked in BOM.txt) and one as an Excel file in the repository. Can we deprecate the Excel file?

At every step in the software the open ephys just crashes, while the green lights keep flickering. When trying to find the board, it crashes, then if by miracle it finds it, it will not find the headstage or it will crash again finding it. Then if you are patient enough to get to this step, it crashes during the impedance measurements or it makes just weird measurements.

http://www.adafruit.com/products/1379

http://www.adafruit.com/products/1378

(This might simplify that aspect of the design...)

There seems to be some bleeding from the status LEDs to the DAC out, we're not completely clear on why this happens yet.

We were debugging camera signaling issues yesterday, and finally discovered that our input source had open-collector logic, and so the pull-down resistors on the TTL lines are problematic. Why pull-down rather than pull-up?

Our acquisition board (v2.1, board 39) is emitting a very annoying high pitched tone once initiated from the GUI. It doesn't depend on the connected headstages, as far as I can tell, but slightly changes in frequency and amplitude when you start the acquisition, but won't stop afterwards unless you disconnect the power plug.

Waving the microphone over the board hasn't given me an exact source yet, but I could try to do so in a more systematic manner if needed.

The images of the populated acquistion board at the bottom of this page are broken links:
https://open-ephys.atlassian.net/wiki/display/OEW/Acquisition+Board

On a related note, this image is out-of-date. This board is marked v2.1 but the current Gerber files are v2.2, and the board looks noticeably different now.
https://github.com/open-ephys/acquisition-board/blob/master/images/acquisition-board-populated.png

Also, I added 2 screenshots to the following wiki page, under "Step 3".
https://open-ephys.atlassian.net/wiki/display/OEW/Building+it+from+scratch
However I used a temporary solution of placing the images in the Public share of my personal dropbox account and linking the wiki to my dropbox. What is the preferred place to upload images to? I couldn't find any Atlassian resource for hosting images.

We've been having trouble with the Digital In channels (a constant noise across all channels), and have also noticed that the LEDs were not consistently working. We suspect that this is a hardware issue with our board, and the production delays mean that we really hope we'll be able to track down the problem ourselves!

We noticed that the both the +5VD_1 testing pin and the 5VA testing pin weren't giving us 5V- they were giving us something significantly lower instead.

Does anybody know the power sequence for the acquisition board? For example, are the +5VD_1 and +5VA testing pins powered by the 5VA and 5VD regulators?

We're trying to track down the specific parts to replace, and we think we found that both of these regulators aren't giving us the right output, but aren't sure whether the next step is to replace the regulators (which, as far as I know, don't break easily, and are also out of stock) or whether this is just a sign that there's a problem elsewhere in the circuit.

Is this problem potentially the result of faulty regulators, or does anyone have other suggestions for the next step?

I've attached a screenshot of what the TTL channel noise looks like during a recording.

Thanks,
Jared

Hi everyone, My experiment needs more than 256 event code, so I want to add the number of digital input channels to 16. Could you please give me any advice? Thank you!

The solidworks stl export seems to have a bug where the scale of exported models is off by a factor of ~10. I pulled the STL files for now (b67f11b). Can someone else try replicating this, maybe it's specific to my version of solidworks. We have the 2013 version here.

In the meantime, use the .sldprt or .igs files.

I was wondering whether It would make sense to include some sort of self-resetting fuse / polyfuse on the power rails to protect the FPGA from the occasional shorting. Alternatively TI offers some eFuses (e.g TPS2596 or for the high voltages TPS2660 with cool circuit breaking func) where users could later change the overvoltage/undervoltage & overcurrent settings by changing some resistors? Moreover these parts have somr monitor outputs which at least could light up a big red LED to signal a problem.
This is now the second time I see an OpalKelly FPGA going up in smoke in our lab. One, by accidentally applying +12V for a brief time (so OpalKelly has NO onboard overvoltage protection ...) and yesterday I just realized that the bare USB2.0 FPGA is not recognized at all and if connected to the AQC board one of the TI LJ245's (upper FPGA side one) gets very hot (so presumably some damage on both parts). I guess I could have connected the populated I/O adapter to the DAC out port for some time ... ;(

Well just a thought ....

Best,
Andreas

Dear all,
It is compatible the open ephys adquition board https://open-ephys.org/acq-board with the intan RHD 128-channel headstage https://intantech.com/RHD_headstages.html?tabSelect=RHD128ch&yPos=0 ?

Thanks!

Recently had a problem where all event channels were set high regardless of digital input. This issue seemed to occur randomly without any warrant.

Hi there,
I thought I could feed the signal of one recorded channel in 'real-time' over the audio jack on the acquisition board to a window discriminator and do some collision experiments. But unfortunately I only have some maybe 250 kHz @ 20 mV noise there. So no modulation regardless whats going on on the channel. My board is made from the plans of January 2014 and I am using the 0.34 GUI. Any help?
Best,
Andreas

Encountered a problem (easily solved) when trying to load a config file for the channel map. After adding the FPGA (everything great, 64 channels on port d found) and the channel map node, It did not automatically select/highlight port "d" on the channel map. If you find "a" highlighted on channel map and click on the icon to load a config file, you receive such error on the terminal window: X returned BadValue (integer parameter out of range for operation) for operation X_ConfigureWindow. The whole open ephys window is then frozen.

Hi all,

we are using the impedance test feature to check the status of our probes before implantation. This works well with the 16-channel Intan head stage and reports 20-30 MOhm in open circuit and ranges in the kOhm range when a probe is connected.
However, when using the 32-channel Intan head stage, all impedance measures are around 1kOhm and don't change any further when connecting a probe. When putting a contact on ground the impedance falls to about 400 Ohms but there seems to be a problem with correctly detecting higher impedance.

Is there anything we can do about this? Is there a setting to change from the 16 to the 32 channel headstage for the impedance test to work correctly?

Thank you and best regards,
Simon

we are use the open ephys system to acuquire the multichannel neuronal cells of animals when the acoustic stimuli is broadcasted. In order to analyze the evoked response, we need acquire the synchronized signal of the acoustic stimuli.
But it doesn't work when we connected the analog input signal to the hardware of the "open ephys", the computer cannot detect the synchronized stimuli. Would you like to help me find the solution method?

the input synchronized stimuli is between 0-3v. But we can see nothing on the destination channel.

qq103320734
[email protected]

Hi,

When recording and streaming inputs from the ADC, with no headstage attached, it works for a while but then freezes and I get this error in the terminal streaming continuously until I stop the acquisition:
[open-ephys] ERROR Error in Rhd2000EvalBoard::readDataBlock: Incorrect header.

Thanks for any help you can give,
Stefan

Hi OpenEphys Team,

We have been encountering a strange issue that we think is originating from the board. Below is a screenshot of a single channel data acquired from a 64 ch linear probe with Intan headstage. The data was sampled at 30 kHz in Bonsai and rescaled from binary unit16 to µV, time is in seconds. As you can see, there is a "clipping" or "step-like" noise. It seems to persist throughout all the recordings & in particular in the bottom ~16 channels or so.

The reason why we think it has to do with the board (and not Bonsai) is since we see a similar pattern of noise in the OpenEphys GUI, and we even see it in another other board using Intan headstage for tetrodes. The unaffected channels have great signal, however. Obvious sources of external noise have been reduced as much as possible (Faraday cages, anti-static, grounding).

Since it looks like discrete chunks of data being out of place, my initial thought is this could be something to do with the multiplexing? Any advice or fixes for this issue would be greatly appreciated.

Thanks!