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or1k-ipxact

IP-Xact files for OpenRISC-based systems

or1k_bootloaders

OpenRISC 1000-compatible bootloaders

pdklite

qspiflash

A set of Wishbone Controlled SPI Flash Controllers

reset_test

Reset demo for blog post

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

riscv-formal

RISC-V Formal Verification Framework

riscv-isa-manual

RISC-V Instruction Set Manual

riscv-opcodes

RISC-V Opcodes

salsa20

Sals20 Stream Cipher core in Verilog

sd-card-controller

WISHBONE SD Card Controller IP Core

serv

SERV - The SErial RISC-V CPU

simple_spi

SPI core

sky130_sram_macros

spi_ram_loader

SPI RAM loader

stream_utils

Utility functions for data streams

subservient

Small SERV-based SoC primarily for OpenMPW tapeout

subservient_wrapped

The Subservient processor wrapped together with some memory for inclusion in the Caravel user project area.

swerv_eh1

A directory of Western Digital’s RISC-V SweRV Cores

symbiflow-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

teroshdldoc

TerosHDL documentation

tinyfpga-bootloader

An open source USB bootloader for FPGAs

tinyfpga-bx

tinyfpga_bx_usbserial

USB Serial on the TinyFPGA BX

tt02-serv

uart16550

UART 16550 core

usbcorev

A full-speed device-side USB peripheral core written in Verilog.

verilatio

A protocol for communicating with HDL simulations over websockets

verilog-axis

Verilog AXI stream components for FPGA implementation

verilog-dsp

Verilog digital signal processing components