olagrottvik / bust Goto Github PK

f2b8fe0 introduced bug, where async reset signal is not referenced in sensitivity list

tb fails for pulse registers with stall longer than the pulse length

check names of:
entity
package
register
field

v0.9.1 generates the line:
signal ipb_pulse_regs : t_<mod_name>pulse_regs := c<mod_name>_pulse_regs;
in the tb even though no pulse regs exist. this fails the compilation as the type and constant does not exist.

The tool should be able to handle the entire bus system, with all its modules at once.

When module's address length matches the bus' address length, addresses containing baseline will not be matched.

add registers with pulse-mode. asserted for one clock cycle then returning to reset value

Add possibility for field reset and description value.
A register with fields should obtain reset value from the fields' reset values

Check for possibility of creating the module.vhd file without overwriting logic created by user. I guess the previous version must also be provided in this case, so that the files can be compared somehow.

generate header files that defines register offsets for C. May also be applicable for Python, but not strictly critical. C is prioritized in this case.

Add the possibility for an additional base offset generic that increments the base address based on the original value. The increment value must also be a variable field.

This will be helpful when instantiating identical modules but don't want to increase source code, documentation, etc

Add generation time stamp on pdf documentation. Also, it would be nice with a version number.

Simple way to add, edit or remove registers, and update the JSON file

To avoid using interconnects IPs (e.g. Xilinx Interconnect IP), generate pure-VHDL interconnects with clock-domain crossing support, etc, for all bus types.

not checking whether rw or ro registers are actually used, and therefore when no RO or RW regs are implemented, will still generate structures that are not needed

Wishbone support can be added by editing the Bus class function returnBusPkgVHDL() and Module class function returnRegisterPIFVHDL()

Make it optional to combine the axi interface signals in a record. Avoiding to use a record will enable Vivado to detect the port as an axi interface, and simplifies connecting in block design GUI.

The software flow has at this moment no automated testing - this must be improved. Also, only one python version is used for manual testing - this must be improved!

add the possibility of adding a length (in clock cycles) for the pulse registers

• Replace cursesmenu with something thats faster

• Base address editor menu part

• Move registers

• Edit registers

• Move fields

• Edit fields

The application should automatically provide a testbench to ensure that the register communication works as intended

Create setup.py, init.py, manifest.ini and scripts for versioning, etc

See http://the-hitchhikers-guide-to-packaging.readthedocs.io/en/latest/quickstart.html

Also consider name-change, bust?

If the master tries to read or write a register that does not exist in the slave spec: transmit a SLVERR on the correct response channel.

areset_n is not in the sensitivity list in process p_mm_select_write

wstrb, awprot and other signals that are not used should be removed from axi package record type. This will resolve warnings in vivado like the following:

[Synth 8-3331] design example_module has unconnected port axi_in[wstrb][3]

add choice for auto-assigning new addresses, e.g. after a register removal

If module register data width is the same as the axi interface, an null assignment is created when masking the "remaining" data bits as zero

simulation fails because of missing signal type definition when the module does include all types
Error: ../tb/global_regs_ipb_pif_tb.vhd(36): (vcom-1136) Unknown identifier "t_global_regs_pulse_regs".

Yup, it's missing...

add a feature to stall the bus for a specific amount of clock cycles for access to certain register or certain module

Add .hpp files that utilizes namespace

to differentiate between generic module packages, add pif to the bus pkg. this way it will be easier to update a module with logic already generated.