After installing, I get the following error when trying to run:

-bash: /usr/bin/ipxact2systemverilog: .: bad interpreter: Permission denied

The executable has the following permissions:
-rwxr-xr-x. 1 root root 226 Mar 2 13:31 /usr/bin/ipxact2systemverilog*

Both python 2.7.5 and 3.6.3 are installed and working.

Any help?

If there are several .xml files in a map, describing registers, after running ipxact2rst, each .rst file begins with :

Register description

Registers

It would be an improvement, if instead we could have the real name of the register, as describe in the xml document at:
spirit:addressBlock
spirit:namefpi_registers</spirit:name> <== this name (fpi_registers) should be the header of the .rst file.

Hi,

I'm trying to run the tool but it fails when trying to validate the ipxact xml file.
the component definition in my file contain several schema used, and it looks the tool doesn't recognize it.

Can anyone help me where and how can I add it?
This is the schema difinition in the file:
<ipxact:component xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014" xmlns:kactus2="http://kactus2.cs.tut.fi" xmlns:ns2="http://kactus2.cs.tut.fi" xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014 http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

Hello. I'm using your project and I have a question. It would be nice if you can help me.
The main problem is that the parser fails if xml file has no attributes (for example, a memoryMap). Is there any way to make the parser work even if there are no attributes in a file?

Thank you for answer.

Hi,

The topic ip-xact could be addded to this repo.
https://github.com/topics/ip-xact

br,

Hi @oddball ,

I am currently in the process of integrating this generator in a Systemverilog project. We plan on using cocotb alongside verilator to make our test benches and test our code. While trying your tool, I had some issues compiling the generated systemverilog code. If we look at the generated example from this repo, the compiler throws these errors.

1. The first one is a simple array assignment issue:

Unsupported: Replication to form 'int$[0:7]' data type: ... In instance example
   22 | const int example_regAddresses [8] = {

The fix is simply to add an apostrophe before the first bracket of the array assignments, like this:

const int example_regAddresses [8] = '{
     reg0_addr,
     reg1_addr,
     reg2_addr,
     reg3_addr,
     reg4_addr,
     reg5_addr,
     reg6_addr,
     reg7_addr};

source: https://verificationguide.com/systemverilog/systemverilog-fixedsize-array/ (see array assignment section)

This change needs to be made for the example_regNames and example_regUnResetedAddresses arrays as well.

2. The second one is simply a type specification issue.

In the example_regUnResetedAddresses array, you have an array of reg type where you set values like 1 and 0. You need to specify the bit width to insure proper allignment. By default, the compiler doesn't know if the value is on 1 bit, 8, 16, etc...

The fix would be this:

const reg registers_regUnResetedAddresses [8] = '{
   1'b0,
   1'b0,
   1'b0,
   1'b0,
   1'b0,
   1'b1,
   1'b1,
   1'b0};

The 1'bX tells the compiler that is set on one bit.

3. The last one is bit more complex allignement issue:

Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's SEL generates 6 bits.
                                                                                                                                               : ... In instance example
  127 |          reg2_addr: r = registers.reg2;

The same thing goes for reg7. The issue is that both of these arrays are not the same width of the other registers. All other registers have a width of 32 bits. For example, reg2 is 6 bits, you therefore need to supply where those 6 bits are.

The fix would be something along the lines of this:

function bit [31:0] read_registers(example_struct_type registers,int address);
      bit [31:0]  r;
      case(address)
         reg0_addr: r = registers.reg0;
         reg1_addr: r = registers.reg1;
         reg2_addr: r[$bits(registers.reg2)-1:0] = registers.reg2; <---
         reg3_addr: r = registers.reg3;
         reg4_addr: r = registers.reg4;
         reg5_addr: r = registers.reg5;
         reg6_addr: r = registers.reg6;
         reg7_addr: r = registers.reg7;
        default: r =0;
      endcase
      return r;
endfunction

The $bits() function is something similar to a sizeof in c/c++. This should also be done on the write_registers function on the data part, since it is supplied as 32 bit wide parameter.

Would like this package to generate C code. If someone could provide an example ipxact xml file and corresponding c code, it should be easy enough for me to add generation of C code.

Hi oddball.

Firstly, I wanted to say how great this tool is that you have created. I have managed to get all the toolchain working.

I was wondering if you or anyone else could recommend a ipxact schema editor to create my own xml register map schema? I tried using Kactus2 but it doesn't seem to support the older 1.5 schema that the ipxact2systemverilog module uses.

Thanks

If 2 identical enum fields are declared in the XML, there will be 2 different enumerated types generated.

Proposed solution is to only declare an enumerated type, if there are no identical enum declared already. Should be easy to implement.

When translating an .xml file to .rst file for an ;xml file containing the html encoding for linefeed
the resulting ;rst file is not correct anymore for later translation to html via sphinx-build.

Example:
spirit:descriptionThis is a test, trying to spread it out over several lines This should come on next line</spirit:description>

Output:

:Description: This is a test, trying to spread it out over several lines
This should come on next line

Hi There,

Just started using this project.. nice work!

When validation failed there is no specific error printed to the user.
I've worked with XML files allot but never with a schema.. I didn't know what was wrong with my file.

Suggest to add this snippet so the user is not left in the dark and can fix whatever is wrong (to validate.py):

if not result:
    print(schema.error_log)

I've never used github .. can I just commit this change?

any help / opinion is welcome !!

thanks, Gal.

https://github.com/MikePopoloski/slang