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License: GNU General Public License v2.0
Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
License: GNU General Public License v2.0
Running arachne on counter.v from tutorial 4 (the 26 bit counter) results in a fatal error due to missing set_io constraints. The counter.v file contains:
module counter(input clk, output [25:0] data);
while the .pcf contains only pin destinations for the first four bits:
set_io data[25] 96
set_io data[24] 97
set_io data[23] 98
set_io data[22] 99
set_io clk 21
Leading to arachne throwing up a fatal error: Missing 22 set_io constraints.
Detect if the assembler program has duplicated labels. When a label is inserted it should be checked that there is not already that label in the dictionary
Hola. He visto en varios capítulos que en los if
hay que poner else
y cubrir todos los casos en los case
para tener un circuito combinacional y que si no es así el sintetizador puede inferir registros. Creo que intuitivamente entiendo a qué se puede referir pero no estoy seguro y quizá otra persona no lo entienda. Creo que añadir esa explicación y las consecuencias que tiene mejoraría el tutorial. Al menos se comenta esto en los capítulos 11 y 12. Gracias.
Es un detalle pequeño, pero mientras los datos en el esquema del multiplexor son 1001 y 0110 en el código generado y pruebas son 1010 y 0101.
Sugiero cambiar los datos en las imágenes si se desea. Si no se entiende perfectamente y se puede cerrar la issue ;)
(estoy disfrutando como un enano de nuevo repasando los circuitos digitales.)
Buenas,
Creo este "issue" para comunicar el hecho de que en los makefiles presentes en el tutorial de ICESTICK, la siguiente línea:
#-- Compilar
iverilog $^ -o $(NAME)_tb.out
hace saltar en mi macOS el error "-o: No such file or directory". Cambiando el comando de la siguiente manera:
#-- Compilar
iverilog -o $(NAME)_tb.out $^
el error desaparece. No sé si crear este "issue" es la manera correcta de comunicar este suceso (que reconozco que igual no es un error porque yo soy un principiante en el uso de compiladores desde la línea de comandos). En caso de que no lo sea, disculpas.
Por otro lado, estaría contento de crear "merge requests" cambiando los "makefile" donde me encuentro el error, pero no lo he hecho nunca y de nuevo no sé si es la forma correcta de proceder.
Un saludo,
Nico
Hola @Obijuan :
He estado echando un vistazo al tutorial y me ha llamado la atención la calidad de las figuras, como por ejemplo esta. He tratado de buscar alguna referencia a la herramienta utilizada para su elaboración, pero no he encontrado ninguna en la wiki ni en la web.
Por ello, quisiera preguntarlo y al mismo tiempo sugerir que se añada (de forma más explícita, si ya está y no lo he visto). Me interesa especialmente (además de la licencia) saber cuánta intervención 'humana' ha sido requerida para pulirlas. ¿Se han añadido todos los elementos a mano? ¿Se he generado un boceto automáticamente a partir de las fuentes y después se ha completado? ¿Se ha realizado todo automáticamente?
Un saludo
Hola
He encontrado lo que creo que es un fallo de coherencia entre el esquema del componente y su programación en verilog.
En el esquema se coge dout e inmediatamente se niega, siendo tanto din como data negada.
Mientras que en el código de verilog se hace correctamente, asignando dout a data antes de negación y din a su negación.
Creo que la puerta not debería estar junto antes de la entrada de din para no afectar a data.
Adjunto imagen.
¡Un saludo!
It is too long. Better split it into subfunctions
Hi all,
I am trying to add a Reset input to a JK flip-flop in verilog. The JK itself works properly, however when I've added the Reset input an error appears saying "errors detected in design"
I am new in verilog. Please find below the code that I am using
reg q = INI;
if (R == 1)
q <= 1'b0;
else
always @(posedge clk)
if (J == 0 && K == 1 )
q <= 1'b0;
else if (J == 1 && K == 1)
q <= ~q;
else if (J == 1 && K == 0)
q <= 1'b1;
Can you help me?
Thank you.
Olatz
Sorry this is in English.
This is what happens when I try 'make sint' in T01-setbit:
[~/open-fpga-verilog-tutorial/tutorial/ICESTICK/T01-setbit]$ make sint
yosys -p "synth_ice40 -blif setbit.blif" setbit.v
/----------------------------------------------------------------------------
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2015 Clifford Wolf [email protected] |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
----------------------------------------------------------------------------/
Yosys 0.5 (git sha1 c3c9fbf, gcc 5.2.1-15 -O2 -fstack-protector-strong -fPIC -Os)
-- Parsing setbit.v' using frontend
verilog' --
setbit.v' to AST representation. Generating RTLIL representation for module
\setbit'.-- Running command `synth_ice40 -blif setbit.blif' --
ERROR: No such command: synth_ice40 (type 'help' for a command overview)
Makefile:41: recipe for target 'setbit.bin' failed
make: *** [setbit.bin] Error 1
Looking through the documentation for yosys, it appears that there is a 'synth' command and a 'synth_xilinx' but no 'synth_ice40'. Did I miss something?
Thanks,
Matt
Hi Obijuan,
first: compliments for your Tutorial. Best Tutorial on Verilog with very nice examples.
I have a question on T27-Memoria ROM generica.
In genrom.v you use posedge clk to read ROM
In genromleds.v you use negedge clk to advance addr.
Why do you mix posedge and negedge clk in one project.
In T22-Reglas de diseno sincrono you say, that it is not a good Idea to use both edgelevel detection.
Is it wrong to use only posedge on genrom.v and genromleds.v?
Greetings
Micha
Verbose mode can be enabled via -v, --verbose
option
yosys -p "synth_ice40 -blif .pioenvs\icestick\hardware.blif" -q src\countsec.v
ERROR: Can't open include file `divider.vh'!
*** [.pioenvs\icestick\hardware.blif] Error 1
================================= [ERROR] Took 1.72 seconds =================================
The terminal process terminated with exit code: 1
Terminal will be reused by tasks, press any key to close it.
I am having problems by charging programs on de Icezum Alhambra. It seems like something is not correct with the drivers because every time I try to charge a code apears: "Icezum Alhambra not conected". Using Mac OS Mojave.
Best regards
Github now allow to use a repository docs
folder as source for the project Github pages. This would allow too to also have the pages prepared to generate a Gitbook book, so the tutorial could be stored as a PDF file.
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