nienfengyao / armv8-bare-metal Goto Github PK

Hello,

We are trying to generate 4 timer based interrupts similar to given in the code with different IRQ numbers using qemu. In the code we can see IRQ number 27 is being used.

Can you please help us with generating/configuring these 4 timer based interrupts ?

Hello, if I run with the string:
qemu-system-aarch64 -machine virt,gic_version=3 -cpu cortex-a57 -nographic -kernel kernel.elf
Several exceptions are raised.

I have tried to print the content of ICC_IAR1_EL1 register in order to understand WHICH exception, by adding to aarch64.* the following header and function:
uint32_t raw_read_icc_iar1_el1(void)

{
	uint32_t icc_iar1_el1 = 0;
	__asm__ __volatile__("mrs %0, s3_0_c12_c12_0\n\t" : "=r" (icc_iar1_el1) :  : "memory");
	return icc_iar1_el1; 
}

The output did surprise me (the following lines are repeated several times:

An exception occurs:
exc_type: 0x00000000 00000011
SP: 0x00000000 40FFFF90
Exception Handler! (
	Current EL = 0x00000000 00000004	exc_type : 0x00000000 00000011
	ICC IAR1 EL1 = 0x00000000 000003FF
AARCH64_EXC_SYNC_SPX)

So the INTID of the exception is 3FF, basically 1023, so a SPURIOUS interrupt. A spurious interrupt means that there are no enabled INTIDs in the pending state, or all INTIDs in that pending are of insufficient priority to be taken. A typical scenario, according to ARM's guide, is that a spurious interrupt is generated when polling the IARs, this value indicates that there are no interrupts to available to acknowledge.

Basically, I have 2 questions:

1. Why does option ",gic_version=3" lead to several spurious interrupt? (I need this option or I can't print ICC_IAR1_EL1 register).
2. Why in the output "exc_type" is different by the content of ICC_IAR1_EL1?

Thanks