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dnn_neurosim_v1.3's Introduction

DNN+NeuroSim V1.3

The DNN+NeuroSim framework was developed by Prof. Shimeng Yu's group (Georgia Institute of Technology). The model is made publicly available on a non-commercial basis. Copyright of the model is maintained by the developers, and the model is distributed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International Public License

🌟 This is the released version 1.3 (Mar 22, 2021) for the tool, and this version has improved following inference engine estimation:

1. Validate with real silicon data.
2. Add synchronous and asynchronous mode.
3. Update technology file for FinFET.
4. Add level shifter for eNVM.

👉 👉 👉 In "Param.cpp", to switch mode:

validated = true;           // false: no calibration factor     // true: validated by silicon data
synchronous = true;         // false: asynchronous    	        // true: synchronous, clkFreq decided by sensing delay

🌟 This version has also added three default examples for quick start:

1. VGG8 on cifar10 
   8-bit "WAGE" mode pretrained model is uploaded to './log/VGG8.pth'
3. DenseNet40 on cifar10 
   8-bit "WAGE" mode pretrained model is uploaded to './log/DenseNet40.pth'
5. ResNet18 on imagenet 
   "FP" mode pretrained model is loaded from 'https://download.pytorch.org/models/resnet18-5c106cde.pth'

👉 👉 👉 To quickly start inference estimation of default models (skip training)

python inference.py --dataset cifar10 --model VGG8 --mode WAGE
python inference.py --dataset cifar10 --model DenseNet40 --mode WAGE
python inference.py --dataset imagenet --model ResNet18 --mode FP

For estimation of on-chip training accelerators, please visit released V2.1 DNN+NeuroSim V2.1

In Pytorch/Tensorflow wrapper, users are able to define network structures, precision of synaptic weight and neural activation. With the integrated NeuroSim which takes real traces from wrapper, the framework can support hierarchical organization from device level to circuit level, to chip level and to algorithm level, enabling instruction-accurate evaluation on both accuracy and hardware performance of inference.

Developers: Xiaochen Peng 👭 Shanshi Huang 👭 Anni Lu.

This research is supported by NSF CAREER award, NSF/SRC E2CDA program, and ASCENT, one of the SRC/DARPA JUMP centers.

If you use the tool or adapt the tool in your work or publication, you are required to cite the following reference:

X. Peng, S. Huang, Y. Luo, X. Sun and S. Yu, ※DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies, § IEEE International Electron Devices Meeting (IEDM), 2019.

If you have logistic questions or comments on the model, please contact 👨 Prof. Shimeng Yu, and if you have technical questions or comments, please contact 👩 Xiaochen Peng or 👩 Shanshi Huang or 👩 Anni Lu.

File lists

  1. Manual: Documents/DNN NeuroSim V1.3 Manual.pdf
  2. DNN_NeuroSim wrapped by Pytorch: 'Inference_pytorch'
  3. NeuroSim under Pytorch Inference: 'Inference_pytorch/NeuroSIM'

Installation steps (Linux)

  1. Get the tool from GitHub
git clone https://github.com/neurosim/DNN_NeuroSim_V1.3.git
  1. Train the network to get the model for inference (can be skipped by using pretrained default models)

  2. Compile the NeuroSim codes

make
  1. Run Pytorch/Tensorflow wrapper (integrated with NeuroSim)

For the usage of this tool, please refer to the manual.

References related to this tool

  1. A. Lu, X. Peng, W. Li, H. Jiang, S. Yu, ※NeuroSim simulator for compute-in-memory hardware accelerator: validation and benchmark, *§ Frontiers in Artificial Intelligence, vol. 4, 659060, 2021.
  2. X. Peng, S. Huang, Y. Luo, X. Sun and S. Yu, ※DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies, § IEEE International Electron Devices Meeting (IEDM), 2019.
  3. X. Peng, R. Liu, S. Yu, ※Optimizing weight mapping and data flow for convolutional neural networks on RRAM based processing-in-memory architecture, § IEEE International Symposium on Circuits and Systems (ISCAS), 2019.
  4. P.-Y. Chen, S. Yu, ※Technological benchmark of analog synaptic devices for neuro-inspired architectures, § IEEE Design & Test, 2019.
  5. P.-Y. Chen, X. Peng, S. Yu, ※NeuroSim: A circuit-level macro model for benchmarking neuro-inspired architectures in online learning, § IEEE Trans. CAD, 2018.
  6. X. Sun, S. Yin, X. Peng, R. Liu, J.-S. Seo, S. Yu, ※XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks,§ ACM/IEEE Design, Automation & Test in Europe Conference (DATE), 2018.
  7. P.-Y. Chen, X. Peng, S. Yu, ※NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures, § IEEE International Electron Devices Meeting (IEDM), 2017.
  8. P.-Y. Chen, S. Yu, ※Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing,§ IEEE International Symposium on Circuits and Systems (ISCAS), 2016.
  9. P.-Y. Chen, D. Kadetotad, Z. Xu, A. Mohanty, B. Lin, J. Ye, S. Vrudhula, J.-S. Seo, Y. Cao, S. Yu, ※Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip,§ IEEE Design, Automation & Test in Europe (DATE), 2015.
  10. S. Wu, et al., ※Training and inference with integers in deep neural networks,§ arXiv: 1802.04680, 2018.
  11. github.com/boluoweifenda/WAGE
  12. github.com/stevenygd/WAGE.pytorch
  13. github.com/aaron-xichen/pytorch-playground

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dnn_neurosim_v1.3's Issues

`Gaccumulation` area

Hi, Can you explain why there is a divide by 3 in the following formula:
Gaccumulation->CalculateArea(NULL, globalBufferHeight/3, NONE);
(the above code can be found in chip.cpp, in the ChipCalculateArea function)
@neurosim

Where is the output

After running make it is showing no errors, but the output CSV files are being generated nowhere. I am a beginner at this. Am I missing something? Please help. Thank you.

Transistor width of 1T1R=19.74F is larger than the assigned cell width=6.00F in layout

I have used the following parameters for 1T1R cell (STT-MRAM)

/*** parameters for analog synaptic devices ***/
heightInFeatureSize1T1R = 6;        // 1T1R Cell height in feature size
widthInFeatureSize1T1R = 5.5;         // 1T1R Cell width in feature size
heightInFeatureSizeCrossbar = 2;    // Crossbar Cell height in feature size
widthInFeatureSizeCrossbar = 2;     // Crossbar Cell width in feature size
   resistanceOn = 3.5e3;               // Ron resistance at Vr in the reported measurement data (need to recalculate below if considering the nonlinearity)
resistanceOff = 8e3;           // Roff resistance at Vr in the reported measurement data (need to recalculate below if considering the nonlinearity)

But I am getting the following error while performing inference simulation:
Transistor width of 1T1R=19.74F is larger than the assigned cell width=6.00F in layout

Quick Question

Hello,
I am very interested in Nsim.
When I reviewed your PPA simulator code, I got a quick question.
As I know, you designed calculating function of BUS with overlap optimization, which makes area becomes zero.
But, Why don't you apply the same overlap scheme for HTree.

Thanks for your contribution.
I've learned a lot of things.
Best regards...

`slSwitchMatrix.CalculatePower` in `SubArray.cpp`

Why in SubArray.cpp, in the calculation of power, the first parameter of the following function, which is numRead, is set to zero?
slSwitchMatrix.CalculatePower(0, 2*numWriteOperationPerRow*numRow*activityRowWrite, activityRowRead, activityColWrite);
On the other hand since activityRowWrite is never set, the second argument , which is numWrite, is also zero. So we have neither reads nor writes for slSwitchMatrix.
@neurosim

System requirements (Linux)

Does it support on latest versions of ubuntu or redhat????

The recommended one in manual are (1) Red Hat 7.8 (Maipo), gcc v4.8.5, glibc v2.17,
(2) Ubuntu 16.04, gcc v5.5.0, glibc v2.23.

But It seems this OS are little older.. so is neuroSIM compatible with latest updates in OS

@neurosim @alu75

Array能耗估计

hi,我在Subarray的能耗评估处看到:SubArray.cpp row:1241
// Read
readDynamicEnergyArray = 0;
readDynamicEnergyArray += capBL * cell.readVoltage * cell.readVoltage * numReadCells; // Selected BLs activityColWrite
readDynamicEnergyArray += capRow2 * tech.vdd * tech.vdd * numRow * activityRowRead; // Selected WL
readDynamicEnergyArray *= numColMuxed;
有两个疑问,想请您解答一下:

  1. 好像只计算了BL、WL的动态功耗,没有看到RRAM的器件功耗?
  2. 在inference.py中看到需要中值电导来消除高阻电流带来的影响,在评估功耗时没有看到相关的部分?
    还请您在百忙之中解答一下,多谢了!
    from NeuroSIm的仰慕者

ImportError: cannot import name 'weak_script_method'

I got an error code ImportError: cannot import name 'weak_script_method'.
As below "quantization_cpu_np_infer" has any problem...
Could you give me any advices?

Traceback (most recent call last):
File "DNN_NeuroSim_V1.3/Inference_pytorch/inference.py", line 14, in
from utee import hook
File "/home/ubuntu/DNN_NeuroSim_V1.3/Inference_pytorch/utee/hook.py", line 5, in
from modules.quantization_cpu_np_infer import QConv2d,QLinear
File "/home/ubuntu/DNN_NeuroSim_V1.3/Inference_pytorch/modules/quantization_cpu_np_infer.py", line 5, in
from torch._jit_internal import weak_script_method
ImportError: cannot import name 'weak_script_method'

Questions about AdderTree::CalculateLatency

Hello @neurosim ,
I want to ask about the meaning of the first parameter (numRead) of the AdderTree:: CalculateLatency(void AdderTree::CalculateLatency(double numRead, int numUnitAdd, double _capLoad)), at the line 120 of AdderTree.cpp.

Question 1

At the line 694 of Chip.cpp, Gaccumulation->CalculateLatency(ceil(numTileEachLayer[1][l]netStructure[l][5](numInVector/(double) Gaccumulation->numAdderTree)), numTileEachLayer[0][l], 0);
I want to know why netStructure[l][5] needs to be multiplied by numTileEachLayer[1][l].

Question 2

At the line 489 of Tile.cpp, accumulationCM->CalculateLatency((int)(numInVector/param->numBitInput)*ceil(param->numColMuxed/param->numColPerSynapse), numPE, 0);
I want to know what ceil (param ->numColMixed/param ->numColPerSynapse) means. Moreover, when param->numColPerSynapse is greater than param ->numColMixed, its value (ceil (param ->numColMixed/param ->numColPerSynapse)) is 0, because both parameters are of type int. Is there a bug?

Significant speedup (using CUDA) can be achieved by initialising arrays on the gpu

I have noticed that, for example, torch.zeros_like() do not define a device. A significant speedup can be achieved when one is defining the device to be equal to 'cuda' in those calls:

Currently:

torch.zeros_like(outputOrignal)

Improved:

torch.zeros_like(outputOrignal, device='cuda')

The same is relevant for torch.normal.

The changes would mainly be needed to be applied to: https://github.com/neurosim/DNN_NeuroSim_V1.3/blob/3754e10e939e80b4952ba4e09a3afb7972456fc9/Inference_pytorch/modules/quantization_cpu_np_infer.py

`readLatencyADC` and `CalculateclkFreq`

Hi,
I have 3 questions:

  1. why the readLatencyADC is just set to numColMuxed? I expect it to be initialized to something which its dimension is time like X.readLatency. However, I found numColMuxed just as the number of columns that share same read circuit that does not have any relation with time.

    readLatencyADC = numColMuxed;

  2. In general, I cannot understand what is exactly the CalculateclkFreq. Can you give some description about it?

  3. In the above code snippet there is an if clause. In this cluase, readLatency is calculated by summing up latency of some modules like adc, switchmatrix and so on. The problem is that, unlike the previous if clause, the CalculateLatency method of the modules is not called. So it is expected that latency of the modules, i.e. X.readLatency is equal to zero which is wrong.

@neurosim
@alu75

RuntimeError: CUDA out of memory

I am getting the following error. Anyone having any solution.

remainderQ = (upper-lower)*(remainder-0)+(cellRange-1)*lower # weight cannot map to 0, but to Gmin
RuntimeError: CUDA out of memory. Tried to allocate 1.12 MiB (GPU 0; 22.37 GiB total capacity; 15.87 GiB already allocated; 3.56 MiB free; 787.74 MiB cached)

Thanks

VGG 使用4-bit ADC的error

您好,我在使用你们提供的vgg8.pth,使用inference=1,设置ADC的精度为4-bit,输出结果很糟糕;如果在训练时将inference=1,会导致训练速度很慢。请问在manual中显示4-bit ADC时仍能达到90%左右的准确率,请问是在什么条件下测出来的呢?
由于在inference=1模式下涉及到很多标量运算,如何训练才不至于速度那么慢呢
谢谢!

argument --wl_weight handled as "str" type

These arguments were treated as "str" type (the default value is "int" type, so no problem if not manually set their values like "--wl_weight 4").
By adding a type conversion in quantization_cpu_np_infer.py like this, the bug could be fixed.

self.wl_weight = int(wl_weight)
self.wl_activate = int(wl_activate)
self.wl_error = int(wl_error)
self.wl_input = int(wl_input)

declaration without initializaion

The variable thisTileTotal in function ChipFloorPlan(in Chip.cpp) is not initialized.
With -O3 optimization, it may be right, but without the optimization, the result will be wrong.

Creating network.csv files

Hello, thank you for NeuroSim. I want to implement some other Network like ResNet50 on ImageNet dataset or VGG19 on CIFAR100. What is the suggestive way of creating the Network.csv file for any other network and dataset we use? Is it getting generated through the pytorch .pth models as we define or we create it manually?

Regards

`TileSize > 4*param->numRowSubArray`

Hi, can you explain the reason of this condition (used in chipFloorPlan)?
XTileSize > 4 * param->numRowSubArray
It is logical that TileSize be greater than numRowSubArray, however I cannot understand why 4 is used? it could be a meaningful parameter.
@neurosim

the mapping method from FP32 weight to synaptic condutance

Hello, neurosim, I've learned a lot from Neurosim.
But I have some quick questions about the mapping method from FP32 weight to synaptic condutance,
Firstly,
why don't you use the more common differential method(A signed kernel weight is mapped to the differential conductance of a pair of memristors used in the paper Fully hardware-implemented memristor convolutional neural network(https://www.nature.com/articles/s41586-020-1942-4)?
Secondly,
The fig.18 in DNN_Neurosim_v1.3_manual.pdf is a little bit strange, why 0.8906 mapped to 15 while 0.9187(>0.8906) mapped to 14(<15)? Is there a formula for this mapping method?

Kind Regards,

Joy Kwan

about batchnormalization layer

Hello, I've learned a lot from Neurosim,
But I have a quick question about network architecture:
I didn't see batchnormalization code in any part of code related to network structure definitions, such as modules/ quantization_cpu_np_infer. py and cifar /model.py, Is there no Batchnormalization layer? And why not?
thanks!

can't solve the problem

I'm trying to run the program on windows system. But it will just throw out an error message: ./layer_record_VGG8/trace_command.sh: line 1: ./NeuroSIM/main:No such file or directory when I run inference.py.
No matter I try absolute path or change 'main' to 'main.cpp' or both, it just doesn't work.
While it does exist a main.cpp file in NeuroSIM directory.

ERROR: SubArray Size is too large

Hi,
@neurosim
when i used my net ,I see "ERROR: SubArray Size is too large, which break the chip hierarchey, please decrease the SubArray size! "
What is the reason for this? thanks a lot

Long inference time but short test time (in train.py)

I run the inference.py with VGG8 and cifar10. It takes about 5 mins to finish, which is rather slow because of hardware consideration. But when I run the train.py with inference=1, the testing is very fast. I think the testing part in train.py should do the same things as the inference.py. But why do they require such a large difference in time?

Or since this repo is recommended for inference only, the train.py in this repo is not correct or sth?

Looking forward to any reply. Thanks.

TypeError

Hello,
First of all, I've learned a lot about NeuroSIM. Really thank you.
I've tried NeuroSIM benchmark with inference.py, but I often have difficulties.

Can you help me for the below problem?

I had gotten the below message.

/bin/bash: ./layer_record_VGG8/trace_command.sh: No such file or directory

So I changed last line of inference.py as below.

call(["/bin/bash", './layer_record_'+str(args.model)+'/trace_command.sh']) → call(["/bin/bash"], './layer_record_'+str(args.model)+'/trace_command.sh',shell=True)

And I got the below error.
Do you have any idea on "TypeError: bufsize must be an integer" ?

File "DNS/DNN_NeuroSim_V1.3-master/DNN_NeuroSim_V1.3-master/Inference_pytorch/inference.py", line 152, in
call(["/bin/bash"], './layer_record_'+str(args.model)+'/trace_command.sh',shell=True)
File "/home/ubuntu/anaconda3/envs/pytorch_p36/lib/python3.6/subprocess.py", line 287, in call
with Popen(*popenargs, **kwargs) as p:
File "/home/ubuntu/anaconda3/envs/pytorch_p36/lib/python3.6/subprocess.py", line 629, in init
raise TypeError("bufsize must be an integer")
TypeError: bufsize must be an integer

Question for conductance variation

Thank you for the great tool!

I'm currently using DNN NeuroSim v1.3 to evaluate the off-chip training performance of my memristor.

Have some questions for the conductance variation in the train.py and inference.py file.

  1. Should I use the conductance variation in percentage value in following code?

parser.add_argument('--vari', default=0, help='conductance variation (e.g. 0.1 standard deviation to generate random variation)')

I'm bit curious whether I should use 0.05 or 5 if i have a memristor with 5% cycle to cycle conductance variation.

  1. Is the conductance variation in above argument cycle-to-cycle or device-to-device?

Again, thank you for the great tool.

Confilict in power consumption

Hello,
I am using DNN_NeuroSim for inference part. I am unable to find correct relation between Power consumption and Chip area.For instance, in the NeuroSim, for pretrained VGG8 the power consumption and Chip area are around 0.1 Watt and 120 mm2. Howover, in the same platforms such as ISAAC and PUMA-simulator the power consumption and Chip area are around 65 Watt and 90 mm2. I can not understant this difference. Please help me.

PUMA-simulator: https://github.com/Aayush-Ankit/puma-simulator
ISAAC paper: https://www.cs.utah.edu/~rajeev/pubs/isca16.pdf

Different Result from the Manual

I am currently doing research on the CiM-based accelerator using the NeuroSIM as a tool to calculate essential information. I tried to simulate the NeuroSIM to get the result that would match with the Figure 24 in the User Manual of DNN+NeuroSim Framework V1.3. However, with many attempts and changes in parameters, I still couldn't get the same result as the paper. I was wondering if you could share the param.cpp file that was used to get the final output as shown in Figure 24 in the paper?

Issue in Leakage Power.

Hi,
Thanks for providing your scripts for interested people.

I have a question about the Leakage Power reported by Neurosim. Because there are a lot of intermediate buffers to store the results of each layer, the Leakage Buffer does not seems convenient to me. I have looked at the Buffer.cpp script, and I think the energy consumption for each cell ( wlDecoder, precharger, sramWriteDriver, senseAmp) is missed and just buffer has been considered.

Best Regards,

Mohammad sabri

error when running inference script

Hi,
When I run inference.py, an error is raised after trace_command.sh is called. The error is "free(): double free detected in tcache 2".
My configs are ubuntu 20.04 focal, gcc 9.3, cuda 10.1, cuDNN 7.5.0, python 3.6, pytorch 1.1.0 (according to the suggestions in the user manual).
I appreciate it if you could help me resolving the issue.

accuracy larger than 100%

When testing VGG8, the accuracy output is 1805%.

I added a line in inference.py to manually accumulate the number of data compared:

correct += pred.cpu().eq(indx_target).sum() # this line already exists
total_pred += len(pred) # new added line

And I tried to calculate accuracy by correct/total_pred.
In this way, the result is about 91%, which seems reasonable. Is this way of calculating correct?

Adapting NeuroSim to use Operation Units

Hi @neurosim, great work on the simulator, I've learnt a lot from it, however, I have a question.

Many works that use eNVMs for In-Memory Processing of DNNs have begun using Operation Units (OUs) in order to better exploit sparsity of weight matrices for example. In these works, instead of activating the entire crossbar, only a portion of it (an OU) is activated at a time. My question is, is it possible to simulate this behavior or would it require significant changes to the code?

Thank you

Question for SAR ADC Power Consumption

Hello

First, Thank you for Great Tool!

I have a question about SAR ADC Power Consumption formula from SarADC.cpp

May I wonder how this formula below comes? especially for log2(levelOutput) ?

Column_Power = (0.4710*log2(levelOutput)+1.9529)*1e-6;

I know that log2(levelOutput) is related to resolution of SAR ADC, but I want to know the reason why Column power increases linearly when resolution of SAR ADC increases

Looking forward to your reply!

Questions about HTree::CalculateLatency

Hi @neurosim and @alu75 ,
At line 718 of Chip.cpp, I found that the x_init and y_init of GhTree->CalculateLatency are always 0, which causes the condition "if (((!x_init) && (!y_init)) || ((!x_end) && (!y_end)))" in HTree::CalculateLatency to always be satisfied. And thus, at the same time, x_end and y_end become invalid variables. I'm wondering if this is a bug or if the tileLocaEachLayer is just useless.

Also, at line from 326 to 338 of Chip.cpp, in the calculation of tileLocaEachLayer in ChipFloorPlan, why thisTileTotal is not accumulated from i=0, but from i=1?

SAR ADC 面积估计

hi:
最近在看您的NeuroSim-v1.3,在评估SarADC面积的部分有个地方不太懂,所以想咨询一下,
在SarADC.cpp中有这样一句代码:areaUnit = (hNmos * wNmos) * (269+(log2(levelOutput)-1)*109) + (hPmos * wPmos) * (209+(log2(levelOutput)-1)*73);
有两个问题:

  1. 269,109,209,73这四个参数代表了nmos、pmos的个数吗?是固定的吗?
  2. levelOutput由 SarADC::Initialize的第二个参数_levelOutput传入,该函数在SubArray.cpp的241行sarADC.Initialize(numCol/numColMuxed, pow(2, avgWeightBit), clkFreq, numReadCellPerOperationNeuro)所调用,也就是说levelOutput=pow(2, avgWeightBit),而在ProcessingUnit.cpp中可以看到subArray->avgWeightBit = param->cellBit,综上:areaUnit和cellbit成正比,我的理解是ADC的面积大小应该是和ADC的量化精度有关系的,所以不太理解为什么该部分的代码。

Divide by 2 in `maxLayerInput` computation

Hi, Why there is a divide by 2 in the following line?
maxLayerInput += netStructure[i][IFM_LENGTH]*netStructure[i][IFM_WIDTH]*netStructure[i][IFM_CHANNEL_DEPTH]/2
(could be found in chip.cpp, ChipInitialize function)
@neurosim

`globalBusWidth`

Hi, I cannot understand how the globalBusWidth is calculated?
globalBusWidth += ((desiredTileSizeCM)+(desiredTileSizeCM)/paramnumColMuxed)*numTileEachLayer[0][i]*numTileEachLayer[1][i];

More specifically, my problem is with this part : (desiredTileSizeCM)/paramnumColMuxed)*numTileEachLayer[0][i]*numTileEachLayer[1][i]
@neurosim

signed computation

For the purpose of signed computation, is negative weights are supported by the simulator? If so, could you please explain how it should be implemented in a simulation?
Just for the context: it is very common to perform signed computation using differential conductance of a pair of memristors.

Library missing on "openram.tech"

Hi,

@neurosim
After installation and build the environment with "make", I tried the recommanded command "python inference.py --dataset cifar10 --model VGG8 --mode WAGE". However, I receiced this error:
ModuleNotFoundError: No module named openram.tech

I have installed "openram" library using pip. But pip and conda cannot find the library "openram.tech" ( "pip install openram.tech" or "conda install openram.tech" doesn't work).

Anyone has idea what might be the problem?

Thanks!

how to use other network

Hi, I have learnt a lot from neurosim.

And I tried the examples you provide. But how to simulate other networks like vgg19, densenet121 and more. I download the models from pytorch and it's hard to make it work

VGG 使用4-bit ADC的error

您好,我在使用你们提供的vgg8.pth,使用inference=1,设置ADC的精度为4-bit,输出结果很糟糕;如果在训练时将inference=1,会导致训练速度很慢。请问在manual中显示4-bit ADC时仍能达到90%左右的准确率,请问是在什么条件下测出来的呢?
谢谢!

error when trainning

hi, I just had a error when I set inference=1. Due to the torch version, I commented out @ weak_ script_ Method, I don't know if it will lead to such a bug? Thanks!
Traceback (most recent call last):
File "/Ai-Data/home/users/zhangfeixiang/Desktop/DNN_NeuroSim_V2.1-master/Training_pytorch/train.py", line 159, in
loss.backward()
File "/usr/local/anaconda3/envs/python36/lib/python3.6/site-packages/torch/tensor.py", line 195, in backward
torch.autograd.backward(self, gradient, retain_graph, create_graph)
File "/usr/local/anaconda3/envs/python36/lib/python3.6/site-packages/torch/autograd/init.py", line 99, in backward
allow_unreachable=True) # allow_unreachable flag
File "/usr/local/anaconda3/envs/python36/lib/python3.6/site-packages/torch/autograd/function.py", line 77, in apply
return self._forward_cls.backward(self, *args)
File "/Ai-Data/home/users/zhangfeixiang/Desktop/DNN_NeuroSim_V2.1-master/Training_pytorch/utee/wage_quantizer.py", line 417, in backward
raise e
File "/Ai-Data/home/users/zhangfeixiang/Desktop/DNN_NeuroSim_V2.1-master/Training_pytorch/utee/wage_quantizer.py", line 409, in backward
grad_input = QE(grad_output, self.bits_E)
File "/Ai-Data/home/users/zhangfeixiang/Desktop/DNN_NeuroSim_V2.1-master/Training_pytorch/utee/wage_quantizer.py", line 52, in QE
assert max_entry != 0, "QE blow"
AssertionError: QE blow
Total Elapse: 5.91, Best Result: 0.000%

Error backward:

tensor(0., device='cuda:0')
tensor(0., device='cuda:0')

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