riscv-rust is a RISC-V processor and peripheral devices emulator project written in Rust and compiled to WebAssembly. You can import RISC-V emulator into your Rust or JavaScript project. Refer to the Slides for more detail.

You can run Linux or xv6 on the emulator in your browser. Online demo is here

• Document

• Emulate RISC-V processor and peripheral devices
• Stable as Linux and xv6-riscv run on it
• Linux OpenSBI and legacy BBL boot support
• Runnable locally
• Also runnable in browser with WebAssembly
• Debugger
• You can import RISC-V emulator into your Rust or JavaScript project

• RV32/64I
• RV32/64M
• RV32/64F (almost)
• RV32/64D (almost)
• RV32/64Q
• RV32/64A (almost)
• RV64C/32C (almost)
• RV32/64Zifencei (almost)
• RV32/64Zicsr (almost)
• CSR (almost)
• SV32/39
• SV48
• Privileged instructions (almost)
• PMP

etc...

The emulator supports almost all instructions listed above but some instructions which are not used in Linux or xv6 are not implemented yet. Your contribution is very welcome.

The emulator module is released at crates.io. Add the following line into Cargo.toml of your Rust project.

[dependencies]
riscv_emu_rust = "0.2.0"

Refer to Document for the API.

$ git clone https://github.com/takahirox/riscv-rust.git
$ cd riscv-rust
$ cargo build --release

$ cd riscv-rust/cli
# Run Linux
$ cargo run --release ../resources/linux/opensbi/fw_payload.elf -f ../resources/linux/rootfs.img
# Run xv6
$ cargo run --release ../resources/xv6/kernel -f ../resources/xv6/fs.img

Prerequirements

• Install riscv-gnu-toolchain
• Install riscv-tests

$ cd riscv-rust/cli
$ cargo run $path_to_riscv_tets/isa/rv32ui-p-add -n

See wasm/web

See wasm/npm

Running 64- and 32-bit RISC-V Linux on QEMU

xv6-riscv is the RISC-V port of xv6 which is UNIX V6 rewritten by MIT for x86 in the current C language.

• RISC-V ISA
• Virtio Device
• UART
• CLINT, PLIC (SiFive E31 Manual)
• SiFive Interrupt Cookbook