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透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

Home Page: https://gitlab.com/Multimedia-Processing/Digital-Logic-Design

License: Other

Verilog 72.81% Mathematica 0.05% VHDL 2.96% TeX 0.01% Scilab 3.33% Assembly 7.86% Hack 0.10% C 8.17% JavaScript 0.04% Makefile 1.45% C++ 1.08% Shell 0.63% CMake 0.02% Batchfile 0.01% Python 0.42% Tcl 0.89% Nix 0.18%
vhdl learn fpga altera-cyclone-v-sockit altera-cyclone-iii-de0 verilog hdl soc-kit altera-cyclone systemverilog

digital-logic-design's Introduction

數位邏輯設計

姓名標示-相同方式分享 3.0 台灣 (CC BY-SA 3.0 TW)

姓名標示-相同方式分享 4.0 國際 (CC BY-SA 4.0)

MIT License

吳晨知 著

開始閱讀

  • #E87A90: 需要達成共識。
  • #876633: 需要獲得幫助。
  • #1B813E: 改進與進步。
  • #E83015: 需要修正問題。
  • #33A6B8: 發展領域。
  • #009966: 重要基礎元件。
  • #6699cc: 參考書籍。
  • #ed9121: 與現實關聯性。

digital-logic-design's People

Contributors

julianxia-2020 avatar kunfukung avatar lin-hsuan-ting avatar seraphiejp avatar simonsteven avatar timmy61109 avatar tyugoo avatar yaim4274 avatar

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digital-logic-design's Issues

6-3 多工器與解多工器的實習

  1. 明瞭多工器的原理與電路設計的方法
  2. 明瞭解多工器的原理與電路設計的方法
  3. 學習解多工器與解碼器的互用方式
  4. 學習直接套用制式IC完成所需

暫存器傳遞

撰寫暫存器轉移的內容與相對應檔案，至於章節名稱可能要再詳細看過其他書籍與統整後才能知道該如何整理。

  • 匯流排
  • 傳遞微運算
  • 算術微運算
  • 邏輯微運算
  • 移位微運算
  • 算術邏輯移位單元

6-4 比較器的實習

  1. 學習比較器的原理與電路設計方法。
  2. 了解應用比較器電路。
  3. 學習直接套用制式IC完成所需。

Chapter02 Verilog RTL 程式設計

  • 2.1 Verilog語言與RTL描述
  • 2.2 Verilog描述敘述對應電路
  • 2.3 如何進行RTL設計
  • 2.4 RTL設計要點
  • 2.5 UART序列埠通訊設計實例

8-1 時鐘賣波產生器的實習

  1. 了解時鐘脈波在循序邏輯電路的作用
  2. 學習利用TTL IC或COMOS IS組成脈波產生器
  3. 學習555定時IC的基本原理與應用電路

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