Every discussion/Q&A will be at https://github.com/tkimva/ucr-eecs168. Please use GITHUB page instead of email to ask any question to TA. Labs must be finished on the given time. You have one week for your lab report. If you lab session is Monday and your lab report due is the next Monday (The end of lab). If the lab is multiple sessions lab, like lab 3, 4, and 5, then a week after the last session of each lab is due. Please be sure to include all required deliverables in your lab report. Five lab reports are required to turn in and total score is 100. Team work (Pair design and programming) (limit 2) is allowed but individual lab report is required and those lab reports should not be the same with your pair.
Week | Date | Remark | Description Points |
---|---|---|---|
Week 1 | Pre-Lab - ENGR account checkup / Linux System Basic | ||
Week 2 | Lab/Tutorial 1 - Synopsys Schematic Design (Galaxy Custom Designer)/ Pre-Simulation (HSPICE) | 10 | |
Week 3 | Lab/Tutorial 2 - Synopsys Layout Design (Galaxy Custom Designer) / Design Rule Check (DRC) / Verification (LVS) | Lab1 report due by the end of lab | 15 |
Week 4 | Lab/Tutorial 3 - Post-Simulation with Parasitic Extraction (HSPICE). Simple Hierarchical IC Design (Target Circuit: 4bit full adder) | Lab2 report due by the end of lab. | 25 |
Week 5 | Lab 3 (Continued) - Simple Hierarchical IC Design (Target Circuit: 4bit full adder) | ||
Week 6 | Lab 4 - Complex Hierarchical IC Design (Target Circuit TBA). | Lab3 report due by the end of lab. | 25 |
Week 7 | Lab 4 (Continued) - Complex Hierarchical IC Design (Target Circuit TBA). | ||
Week 8 | Lab/Tutorial 5 - Full Chip Design with RTL (Verilog, Design Compiler/IC Compiler). | Lab4 report due by the end of lab. | 50 |
Week 9 | Lab/Tutorial 5 (Continued) - Full Chip Design | ||
Week 10 | Lab 5 (Continued) - Full Chip Design. Lab report due at the end of lab. | ||
Final Week | No lab | lab5 report due by the end of lab into TA office hour (WCH109). |
- Students who are late less than 10 min are considered tardy. (10% penalty of your lab report grade)
- Students who are late more than 10 min are considered absent. (50% penalty of your lab report grade)
- Any missed lab should be made up within 1 week with 50% penalty, otherwise no credit. Missing a lab is acceptable only when emergency occurs (eg. Medical emergency, doctor letter is required)
- If you finish your lab earlier, you do not need to come to lab, but you have to show your proof-of-completion (simple screenshot) to get permission by email.
- Late submission will not be accepted for your lab report.
- You need to get checkoff your each lab result. If not , you will receive no credit for your lab score even if you submit your lab report.
Each lab report should be individual even if you can do pair design and programming. If I find students cheating on the lab report, I give no credit for lab given report. Then I forward your case to the academic integrity board at UCR.