FPGA many-core processor implementation written in Verilog HDL

Up to 501-core processors are implemented in a single FPGA

• 32bit data/register width processor core version

33 cores implemented, Fmax: 140 MHz / Terasic DE0-CV

171 cores implemented, Fmax: 100 MHz / BeMicro-CVA9

145 cores implemented, Fmax: 200 MHz / Kria KV260

with UART, VGA interface

• 16bit data/register width processor core version

65 cores implemented, Fmax: 140 MHz / Terasic DE0-CV

501 cores implemented, Fmax: 100 MHz / BeMicro-CVA9

http://cellspe.matrix.jp/zerofpga/mini16_manycore.html

An example of parallel processing of the Mandelbrot set