Full PLIC support is not required by the rules/zephyr, PLIC support can be disable in the zephyr option, then machine timer would be used as os tick source. You need to provide then two 64 memory mapped registers for the machine timer as specified in privileged ISM document.

From the rules: "The Zephyr 1.13 release should be used and can only be modified in a way that does not touch the OS core" - however it is not clear what is considered as OS (Zephyr RTOS) core!

if we assume that \zephyr\arch\riscv32\core

belongs to OS core, then we can still modify it indirectly as the files in that folder do use some MACROS defined elsewhere (as example SOC_ERET) if we REDEFINE that macro it would "change" the OS core and could disqualify our entry?

It is also to be assumed that lots of other files belong to OS core - but the set of "core" and not core files is not clear.

Linux license tool has not been recommended to be used for a long time (it was developed initially by Actel), guides exist to help setup libero/environment and license on Linux.

The amount of manual work depends on the linux distribution

How to prevent the ARM core to access eNVM or eSRAM when those resources are used by the softCore in FPGA Fabric?

Getting errors all the time, core0 not found. Clock should be present, changing TCK speed does not help.

rules say in "min requirements" that zephyr app compiled with unmodified GCC from zephyr should be used, but the rules do not say the core may not be usable with other compilers. So very strictly the rules do not specify the compiler for dhrystone, only that -O -fno_inline should be used.

RECOMMENDATION: use mainline unmodified GCC version, if possible without recompiling it from sources.

contest rules say that dhrystone from this github url must be used
https://github.com/riscv/riscv-tests/tree/master/benchmarks/dhrystone
there are 3 files, and we must assume those files can not be modified to comply with the rules.

Those files will calculate benchmark as

Dhrystones_Per_Second = (HZ * Number_Of_Runs) / User_Time;

Where User_Time is mcycle CSR difference, so it is read from counter that runs and CPU clock speed, so it obvious we must define HZ equal to clock CPU frequency. This can be done in util.h
(so we do not need to modify the benchmark sources)

problem is dhrystone result will then be NEGATIVE number.. nonsense!

this is major issue for anyone who would implement execute in place from eNVM or SPI Flash.

FENCE.I test code must reside in writeable RAM

paid version of synplify may produce better results, is it OK for the contest?

by the rules the targets are SmartFusion2/IGLOO and Lattice iCE40Plus, but there is also directly mentioned M2SF025 so it is not clear if design targetting SMALLER FPGA's from the same family would be considered as fulfilling the contest set requirements, as example
[https://shop.trenz-electronic.de/de/TEM0001-01A-010C-SMF2000-FPGA-Modul-mit-Microsemi-SmartFusion2-8-MByte-SDRAM]
would a design running on that qualify?

It is not possible to find documentation for this board, not from Microsemi not from Future website. The only source of technical information about those boards can be reverse engineered from the hello world example projects that uses RISCV softcore (MIV from Microsemi). LED Blinky project yields 404 link.
But the file downloaded a SmartFusion2 demo actually does download the IGLOO2 demo. Well the both boards share the same PCB, so info reverse engineered from igloo2 hello would be valid for the SmartFusion2 board too

Currently, the softcore has to pass the ebreak complience test, but I don't see any sense in this for a softcore which only implement the machine mode / without linux.

Also, it has the side effect of not don't allowing some debugging architecture where the ebreak instruction is natively handled by a debug module into the CPU. (ex : VexRiscv debug module)

Based on the FAQ added on October 26 it is needed to "output messages" on all target boards. So if you have an UPduino or any other UP5K board that does not have on-board UART you need to find to demonstrate "outputting messages".

It is unclear if Morse code as means to output messages is accepted.

This also include verilog attributs to set the cells position.

What rule exactly prevent you to maintaining this repo ?

Does Libero supports Ubuntu? I am unable to get the installer working on Ubuntu 16.04. My system is running an Intel i3 processor and has about 250 GB of free space. Any ideas would be appreciated!

it asks for separate license and does not work, so no way to actually debug anything.

Reported by one user - Creative board VCP not loading, not linux not windows

microsemi can not init BRAM, so the boot code must be either in LUT or then eNVM what is also a problem

The official rules say: "standard RISC-V GCC provided by Zephyr" however from the zephyr installation and online documentation it is not clear what GCC is used, where it is fetched or how it should be configured.

RV32I does not require a PLIC, but Zephyr 1.13 does not run a riscv-privilege build without one, without modification to the Zephyr OS Core.

Can one build a non-riscv-privilege core (as far as Zephyr 1.13 is concerned) - would this not require modification to Zephyr OS core?