🔌 Compact-JTAG to 4-Wire JTAG Bridge
This bridge implements a simple converter to connect compact JTAG (cJTAG) probes to IEEE 1149.1 4-wire JTAG device. cJTAG only uses two wires: a uni-directional clock generated by the probe (TCKC) and a bi-directional data signal (TMSC).
Top Entity
The top entity is rtl/cjtag_bridge.vhd:
entity cjtag_bridge is
port (
-- global control --
clk_i : in std_ulogic; -- main clock
rstn_i : in std_ulogic; -- main reset, async, low-active
-- cJTAG (from debug probe) --
tckc_i : in std_ulogic; -- tap clock
tmsc_i : in std_ulogic; -- tap data input
tmsc_o : out std_ulogic; -- tap data output
tmsc_oe_o : out std_ulogic; -- tap data output enable (tri-state driver)
-- JTAG (to device) --
tck_o : out std_ulogic; -- tap clock
tdi_o : out std_ulogic; -- tap data input
tdo_i : in std_ulogic; -- tap data output
tms_o : out std_ulogic -- tap mode select
);
end cjtag_bridge;clk_i signal) frequency.
clk_i (same clock domain).
db_* are intended for testing/development only.
Hardware Requirements
The bridge requires a module-external tri-state driver for the off-chip TMSC signal (tmsc), which handles the module's
tmsc_i, tmsc_o and tmsc_oe_o signals:
-- TMSC tri-state driver --
tmsc <= tmsc_o when (tmsc_oe_o = '1') else 'Z';
tmsc_i <= tmsc;Simulation
The projects provides a very simple testbench to test the basic IO functions
(sim/cjtag_bridge_tb.vhd).
It can be simulated by GHDL via the provided script:
cjtag_bridge/sim$ sh ghdl.sh
The simulation will run for 1ms using a 100MHz clock. The waveform data is stored to sim/cjtag_bridge.ghw
so it can be viewed using gtkwave:
cjtag_bridge/sim$ gtkwave cjtag_bridge.ghw
A pre-defined waveform configuration file is also provided: sim/wave_config.gtkw
React
Typescript
Django
Laravel
Facebook
Microsoft
Google
Alibaba
D3
Tencent