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This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.

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16-bit-cpu code-execution computer-architecture control-unit cpu-design custom-processor gui-dashboard instruction-set-architecture logic-circuits mips-simulator processor-design simulation user-interface

ceng3010-computer-organization's Introduction

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This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.


Project I: 32-bit MIPS Simulator with GUI Dashboard

The first project is a 32-bit MIPS Simulator with a GUI Dashboard. This project contains a simulator that accurately replicates the MIPS architecture while providing a user-friendly graphical user interface (GUI) for code execution and analysis.

Features

  • Interactive Dashboard: The GUI dashboard provides real-time visualization of key components including General Purpose Registers (GPRs), Program Counter (PC), Hi-Lo Registers, Instruction Memory (IM) and Data Memory (DM), offering insights into the simulation's progress.
  • Branching Support: Full support for both conditional and unconditional branches ensures accurate simulation of branching behavior within the code.
  • Procedure Calls: The simulator effectively handles procedure calls and implementations, replicating the behavior of functions within the MIPS architecture.
  • Supported Instructions:
    • R-Type:
      • add, sub, and, or, xor,
      • mult, div, mfhi, mflo,
      • sll, srl, sra,
      • slt, jr
    • I-Type:
      • addi, andi, ori,
      • lw, lb, sw, sb,
      • beq, bne,
      • lui, slti
    • J-Type:
      • j, jal
  • User-Friendly GUI: The graphical interface enables code input, observation of registers, memory inspection, and other essential fields, making the simulation process user-friendly.
  • Memory Capacity: With total of 1KB allocated for both data and instruction memory, you can explore and visualize their contents directly within the GUI.

In summary, Project I presents a 32-bit MIPS Simulator with a user-friendly GUI Dashboard. This tool accurately replicates 32-bit MIPS architecture, offers a simple platform to run and understand code, supports various instructions including branching, and provides an accessible platform for code execution and analysis. It's a great way to explore and visualize MIPS operations.

ceng3010-computer-organization's People

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ceng3010-computer-organization's Issues

Incorrect Memory Starting Addresses in Project I

Problem:
In Project I, the data memory (DM) and instruction memory (IM) currently start from 0x00000000, which does not match the required memory layout of the MIPS architecture.

Action Needed:
To ensure proper alignment with the MIPS architecture, it's necessary to modify the starting addresses of both DM and IM.

Steps to Resolve:

  1. Adjust the data memory (DM) starting address to 0x10010000.
  2. Modify the instruction memory (IM) starting address to 0x00400000.

By implementing these changes, the project will accurately reflect the memory organization specified by the MIPS architecture.

Implement Labeling for Branching, Jumping, and Procedure Calls in Project I

Problem:
Project I currently does not incorporate labeling for branching and jumping instructions, which consequently leads to the absence of proper procedure call functionality.

Action Needed:
To address this limitation, it's essential to introduce labeling for branching and jumping instructions, enabling the implementation of procedure calls as well.

Steps to Resolve:

  1. Identify the sections of code responsible for handling branching and jumping instructions.
  2. Integrate a labeling mechanism that accurately identifies target locations for branches and jumps.
  3. Utilize the labeling mechanism to enable proper procedure call functionality, aligning with the MIPS architecture's behavior.

By making these enhancements, the project will be able to accurately support branching, jumping, and procedure call operations, significantly improving the overall functionality and completeness of the simulator.

Incorrect Jump and Branch Instruction Formats in Project I

Problem:**
In Project I, there are issues with the current formats of jump and branch instructions. The jump instruction lacks the required pseudodirect addressing format, and the branch instruction does not utilize PC relative addressing as expected by the MIPS architecture.

Action Needed:
To ensure accurate simulation and alignment with the MIPS architecture, it's necessary to revise the formats of jump and branch instructions.

Steps to Resolve:

  1. Identify the relevant sections of code responsible for handling jump and branch instructions.
  2. Update the jump instructions to conform to the pseudodirect addressing format.
  3. Modify the branch instructions to utilize PC relative addressing as specified in the MIPS architecture.

This adjustment will enhance the accuracy of the simulation and ensure that the project correctly reflects the MIPS instruction formats.

Implement Stack Structure and Fix $sp Register in Project I

Problem:
Project I lacks the stack structure that is essential in MIPS architecture, and the stack pointer register ($sp) is not functioning correctly. These issues prevent accurate simulation of the stack-related operations.

Action Needed:
To rectify this, it's important to integrate the necessary stack structure and ensure the proper functionality of the $sp register.

Steps to Resolve:

  1. Introduce the stack structure within the simulation, adhering to the MIPS architecture's stack guidelines.
  2. Update the initial value of the stack pointer ($sp) to 0x7fffeffc in the background registers, ensuring it points to the reserved stack memory.

By making these adjustments, the project will be able to precisely emulate stack-related actions, improving the overall accuracy of the MIPS architecture representation.

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